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參數資料
| 型號： | LTC2754ACUKG-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 28/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QUAD IOUT 52-QFN |
| 標準包裝： | 45 |
| 系列： | SoftSpan™ |
| 設置時間： | 2µs |
| 位數： | 16 |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 52-QFN（7x8）裸露焊盤 |
| 包裝： | 管件 |
| 輸出數目和類型： | 8 電流，單極；8 電流，雙極 |
| 采樣率（每秒）： | * |
| 配用： | DC1546A-ND - BOARD DAC LTC2754-16 |
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LTC2754
9
2754f
PIN FUNCTIONS
VOSADJD (Pin 20): DAC D Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJD produces ΔVOS =
-512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RIND). Tie to ground if not used.
VOSADJC (Pin 21): DAC C Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJC produces ΔVOS =
-512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINC). Tie to ground if not used.
IOUT1C (Pin 22): DAC C Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplier for DAC C (see Typical Applications).
RFBC (Pin 23): DAC C Feedback Resistor. For normal
operation tie to the output of the I/V converter amplier
for DAC C (see Typical Applications). The DAC output
current from IOUT1D ows through the feedback resistor
to the RFBC pin. The impedance looking into this pin is
10k to ground.
ROFSC (Pin 24): Bipolar Offset Network for DAC C. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RINC (Pin 28). The
impedance looking into this pin is 20k to ground.
REFC (Pin 25): Inverted Reference Voltage for DAC C, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFC to RCOMC.
For normal operation tie this pin to the output of reference
inverting amplier (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RINC and RCOMC oating).
RCOMC (Pin 26): Center Tap Point for Reference Amplier
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RINC to RCOMC and from
RCOMC to REFC, respectively (see Block Diagram). For
normal operation tie RCOMC tothenegativeinputofexternal
reference inverting amplier (see Typical Applications).
GEADJC (Pin 27): Gain Adjust Pin for DAC C. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRINC (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RINC (Pin 28): Input Resistor for Reference Inverting
Amplier. The 20k input resistor is connected internally
from RINC to RCOMC. For normal operation tie RINC to the
external reference voltage VREFC (see Typical Applica-
tions). Any or all of these precision-matched resistor
sets (Each set comprising RINX, RCOMX and REFX) may be
used to invert one or more positive reference voltages to
the negative voltages needed by the DACs. Typically 5V;
accepts up to ±15V.
IOUT2C (Pin 29): DAC C Current Output Complement. Tie
IOUT2C to ground.
CLR (Pin 30): Asynchronous Clear Pin. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
RFLAG (Pin 31): Reset Flag Pin. An active low output is
asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
M-SPAN (Pin 32): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S2, S1 and S0 (Pins 33, 34
and 35) to congure all DACs for operation in a single,
xed output range.
To congure the part for manual-span use, tie M-SPAN
directly to VDD. The active output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To congure the part for SoftSpan use, tie M-SPAN di-
rectly to GND. The output ranges are then individually and
dynamically controllable through the SPI port; and pins
S2, S1 and S0 have no effect.
See ‘Manual Span Conguration’ in the Operation sec-
tion. M-SPAN must be connected either directly to
GND (SoftSpan conguration) or to VDD (manual-span
conguration).
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