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參數(shù)資料
| 型號： | LTC2925 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Octal Bus Transceiver With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 四路電源排序器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | LTC2925 |
LTC2924
11
2924f
Details of Resistor Calculations
In this example, the voltage at the IN pins is 0.61V when
the LTC2924 detects that the power supply is On during a
Power On sequence or Off during a Power Off sequence.
The delta voltage,
V, represents the difference:
V = 2.2V – 1V = 1.2V
This delta voltage on R
B
will be equal to the hysteresis
current I
HYS
. Therefore:
V
I
A
HYS
μ
50
The current I
RB
at the Power On voltage of 2.2V is:
R
V
k
B
=
=
=
1 2
.
24
I
V
V
k
A
RB
=
=
μ
2 2
.
–0 61
24
66
During the Power On sequence, I
HYS
= 0, so I
FB
is equal to
I
RB
and R
A
is:
R
A
k
A
=
μ
=
0 61
66
9 2
.
.
V
OFF
Precaution
Use caution if designs call for V
OFF
voltages less than
~0.8V. Many loads stop using significant current below
this level, and the power supply may take a long time to go
below this voltage. If V
OFF
voltages at or less than this
voltage are necessary, consider adding an extra resistive
load at the output of the power supply to ensure it
discharges in a reasonable amount of time.
Selecting the Timing Capacitor
During the Power On sequence, the timer is used to
create a delay between the time one supply reaches the
On threshold and the next supply is enabled. During the
Power Off sequence, the timer is used to create a delay
between the time one supply reaches the Off threshold
and the next supply is disabled. Select the timing capaci-
tor with the following equation:
C
TMR
(F) = t
DELAY
5000
–3
F/s
Leaving the TMR pin unconnected will generate the mini-
mum delay. The accuracy of the time delay will be affected
by the capacitor leakage (the nominal charge current is
5
μ
A) and capacitor tolerance. A low leakage ceramic
capacitor is recommended.
Selecting the Power Good Timer (PGT) Capacitor
During the Power On sequence, the PGT can be used to
detect the failure of a power supply to reach the desired On
voltage. The PGT is enabled each time a power supply is
enabled by the OUT1-OUT4 pins. The PGT is reset each
time an IN1-IN4 pin detects that a power supply is at the
desired On voltage. Select the PGT timeout capacitor with
the following equation:
C
PGT
(F) = t
PGT
5000
–3
F/s
If no PGT is desired, the PGT pin must be shorted to
ground. The accuracy of the PGT timeout will be affected
by the capacitor leakage (the nominal charge current is
5
μ
A) and capacitor tolerance. A low leakage ceramic
capacitor is recommended.
Cascading Multiple LTC2924s
Two or more LTC2924s may be cascaded to fully se-
quence 8,12 or more power supplies. Figures 7 and 8
show how to configure the LTC2924 to sequence 8 and 12
power supplies. To sequence more power supplies, use
the circuit in Figure 8 and add more LTC2924s in the
middle.
Notice that the lastLTC2924 in the cascade string must
have a pull-up resistor on the DONE pin. Any LTC2924 that
is not the firstin the cascade string should have the
hysteresis current setting resistor, R
HYS
, pulled to V
CC
instead of ground. The value of the R
HYS
resistor remains
unchanged. The FAULT pins should all be connected
together and pulled up with a single 10k resistor.
All V
CC
pins for the LTC2924s in the cascade chain must
be connected to the same power supply.
APPLICATIU
W
U
U
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