參數(shù)資料
型號(hào): LTC3525ESC6-3
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.45 A SWITCHING REGULATOR, PDSO6
封裝: PLASTIC, SC70, 6 PIN
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 276K
代理商: LTC3525ESC6-3
LTC3525-3/
LTC3525-3.3/LTC3525-5
7
3525fa
BLOCK DIAGRA
W
PI FU CTIO S
UU
U
SHDN (Pin 1): Logic Controlled Shutdown Input. Con-
nect to a voltage >1V to enable the LTC3525. Connect to
a voltage <0.4V to disable the LTC3525.
GND (Pins 2, 5): Ground.
VIN (Pin 3): Input Voltage. The LTC3525 is powered from
VIN until VOUT exceeds VIN. Once VOUT is greater than (VIN
+ 0.2V typical), it is powered from VOUT. Place a ceramic
bypass capacitor from VIN to GND. A minimum value of
1F is recommended.
VOUT (Pin 4): Output Voltage Sense and the Output of the
Synchronous Rectier. Connect the output lter capacitor
from VOUT to GND, close to the IC. A minimum value of
10F ceramic is recommended. Use 22F for reduced
output ripple. The output disconnect feature disconnects
VOUT from VIN when SHDN is <0.4V.
SW (Pin 6): Switch Pin. Connect an inductor from this
pin to VIN. An internal antiringing resistor is connected
across SW and VIN after the inductor current has dropped
to zero to minimize EMI.
+
+
+
+
3
6
1
2
4
VREF
IPK
COMPARATOR
IVALLEY
COMPARATOR
SLEEP
COMPARATOR
INTEGRATOR
WAKE
TSD
IVAL
VOUT
VIN
SHDN
SW
IPK
ADJUST
GND
5
GND
FB
OFFSET
ADJUST
OFFSET
ADJUST
LOGIC
GATE DRIVERS
AND
ANTI-CROSS
CONDUCTION
WELL
SWITCH
VBEST
VREF
UVLO
THERMAL
SHUTDOWN
VB
SHUTDOWN
STARTUP
UVLO
SHUTDOWN
VREF
VSEL
VOUT
3525 BD
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PDF描述
LTC3525ESC6-3#TRM 0.45 A SWITCHING REGULATOR, PDSO6
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LTC3547EDDB-1#PBF 0.7 A DUAL SWITCHING CONTROLLER, 2700 kHz SWITCHING FREQ-MAX, PDSO8
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