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參數(shù)資料
| 型號(hào)： | LTC3828 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Bus Transceiver With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 雙2相降壓型跟蹤控制器 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 396K |
| 代理商： | LTC3828 |
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LTC3828
3828f
11
inductor current) operation over the widest possible out-
put current range. This constant frequency operation is
not as efficient as Burst Mode operation, but does provide
a lower noise, constant frequency operating mode down
to approximately 1% of the designed maximum output
current.
Continuous Current (PWM) Operation
Tying the FCB/PLLIN pin to ground will force continuous
current operation. This is the least efficient operating
mode, but may be desirable in certain applications. The
output can source or sink current in this mode. When
sinking current while in forced continuous operation,
current will be forced back into the main power supply
potentially boosting the input supply to dangerous voltage
levels—BEWARE!
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within
±
7.5% of the nominal output
level as determined by the resistive feedback divider.
When both outputs meet the
±
7.5% requirement, the
MOSFET is turned off within 10
μ
s and the pin is allowed to
be pulled up by an external resistor to a source of up to
5.5V.
Foldback Current
Foldback current limiting is activated when the output
voltage falls below 70% of its nominal level. If a short is
present, a safe, low output current is provided due to
internal current foldback and actual power wasted is low
due to the efficient nature of the current mode switching
regulator. This function is disabled at start-up.
(Refer to Functional Diagram)
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the FCB/PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator that
operates over a 260kHz to 550kHz range corresponding to
a DC voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal.
The internal master oscillator runs at a frequency twelve
times that of each controller’s frequency. The PHSMD pin
(UH package only) determines the relative phases be-
tween the internal controllers as well as the CLKOUT signal
as shown in Table 2. The phases tabulated are relative to
zero phase being defined as the rising edge of the top gate
(TG1) driver output of controller 1.
Table 2.
V
PHSMD
Controller 1
Controller 2
CLKOUT
GND
0
°
180
°
60
°
OPEN
0
°
180
°
90
°
INTV
CC
0
°
240
°
120
°
The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution
feeding a single, high current output or separate outputs.
Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by the
number of phases used and power loss is proportional to
the RMS current squared. A two stage, single output
voltage implementation can reduce input path power loss
by 75% and radically reduce the required RMS current
rating of the input capacitor(s).
In the G28 package, CLKOUT is 90
°
out of phase with
channel 1 and channel 2.
Constant Frequency Operation
When the FCB/PLLIN pin is tied to INTV
CC
, Burst Mode
operation is disabled and the forced minimum output
current requirement is removed. This provides constant
frequency, discontinuous current (preventing reverse
OPERATIOU
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