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參數(shù)資料
| 型號(hào)： | LTC4098EUDC-3.6#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | BATTERY CHARGE CONTROLLER, PQCC20 |
| 封裝： | 3 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | LTC4098EUDC-3.6#PBF |
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LTC4098-3.6
409836f
Board Layout Considerations
TheexposedpadonthebacksideoftheLTC4098-3.6pack-
age must be securely soldered to the PC board ground.
This is the primary ground pin in the package and it serves
as the return path for both the control circuitry and the
synchronous rectifier.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitor, inductor, and
output capacitor be as close to the LTC4098-3.6 as pos-
sible and that there be an unbroken ground plane under
the LTC4098-3.6 and all of its external high frequency
components. High frequency currents, such as the input
current on the LTC4098-3.6, tend to find their way on the
ground plane along a mirror path directly beneath the
incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
theirnaturalleast-areapath,excessivevoltagewillbuildup
and radiated emissions will occur (see Figure 10). There
should be a group of vias directly under the grounded
backside leading directly down to an internal ground
plane. To minimize parasitic inductance, the ground plane
should be as close as possible to the top plane of the PC
board (layer 2).
The IDGATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset to
theidealdiodeofapproximately10mV.Tominimizeleakage,
the trace can be guarded on the PC board by surrounding
it with VOUT connected metal, which should generally be
less than one volt higher than IDGATE.
Battery Charger Stability Considerations
The LTC4098-3.6’s battery charger contains both a con-
stant-voltage and a constant-current control loop. The
constant-voltage loop is stable without any compensation
when a battery is connected with low impedance leads.
Excessive lead length, however, may add enough series
inductance to require a bypass capacitor of at least 1F
from BAT to GND.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22F may
beusedinparallelwithabattery,butlargerceramicsshould
be decoupled with 0.2
Ω to 1Ω of series resistance.
Furthermore, a 100F MLCC in series with a 0.3
Ω resistor
or a 100F OS-CON capacitor from BAT to GND is required
to prevent oscillation when the battery is disconnected.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the charger
is stable with program resistor values as high as 25k.
However, additional capacitance on this node reduces the
maximum allowed program resistor. The pole frequency at
the PROG pin should be kept above 100kHz. Therefore, if
the PROG pin has a parasitic capacitance, CPROG, the fol-
lowing equation should be used to calculate the maximum
resistance value for RPROG:
R
kHz c
PROG
≤
1
2 100
π
applicaTions inFormaTion
Figure 10. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
409836 F10
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