參數(shù)資料
型號(hào): LTC4210-1CS6
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Hot Swap Controller in 6-Lead SOT-23 Package
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封裝: 1 MM HEIGHT, PLASTIC, MO-193, TSOT-23, 6 PIN
文件頁數(shù): 10/20頁
文件大?。?/td> 246K
代理商: LTC4210-1CS6
10
LTC4210-1/LTC4210-2
421012f
parasitic oscillations frequently associated with the power
MOSFET. In some applications, the user may find that R
G
helps in short-circuit transient recovery as well. However,
too large of an R
G
value will slow down the turn-off time.
The recommended R
G
range is between 5
and 500
.
Usually, method 2 is preferred when the input supply volt-
age is greater than 10V. R
G
limits the current flow into the
GATE pin’s internal zener clamp during transient events.
The recommended R
C
and C
C
values are the same as
method 1. The parasitic compensation capacitor C
P
is
required when 0.2
μ
F < load capacitance C
L
< 9
μ
F, other-
wise it is optional.
Parasitic MOSFET Oscillation
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping at
power-up or during current limiting. The first type of os-
cillation occurs at high frequencies, typically above 1MHz.
This high frequency oscillation is easily damped with R
G
as
mentioned in method 2.
The second type of oscillation occurs at frequencies be-
tween 200kHz and 800kHz due to the load capacitance
being between 0.2
μ
F and 9
μ
F, the presence of R
G
and R
C
resistance, the absence of a drain bypass capacitor, a com-
bination of bus wiring inductance and bus supply output
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load ca-
pacitance below 10
μ
F, the second choice is connecting an
external C
P
> 1.5nF.
APPLICATIOU
If a 7m
sense resistor with
±
1% tolerance is used for
current limiting, the nominal current limit is 7.14A. From
Equations 2 and 3, I
LIMIT(MIN)
= 6.22A and I
LIMIT(MAX)
=
8.08A. For proper operation, the minimum current limit
must exceed the circuit maximum operating load current
with margin. The sense resistor power rating must exceed
V
CB(MAX)2
/R
SENSE(MIN)
.
W
U
U
V
CC
SENSE
R
0.007
Q1
Si4410DY
Q1
Si4410DY
V
IN
5V
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**USE C
IF 0.2
μ
F < C
< 9
μ
F,
OTHERWISE NOT REQUIRED
6
5
C
L
4
R
C
100
C
10nF
GATE
LTC4210*
(2a)
Method 1
V
CC
SENSE
R
0.007
R
G
200
C
**
2.2nF
V
IN
12V
V
OUT
V
OUT
6
5
4
R
C
100
C
10nF
4210 F02
GATE
LTC4210*
(2b)
Method 2
+
C
L
+
Figure 2. Frequency Compensation
Frequency Compensation
A compensation circuit should be connected to the GATE
pin for current limit loop stability.
Method 1
The simplest frequency compensation network consists
of R
C
and C
C
(Figure 2a). The total GATE capacitance is:
C
GATE
= C
ISS
+ C
C
Generally, the compensation value in Figure 2a is suffi-
cient for a pair of input wires less than a foot in length.
Applications with longer input wires may require the R
C
or
C
C
value to be increased for better fault transient perfor-
mance. For a pair of three foot input wires, users can start
with C
C
= 47nF and R
C
= 100
. Despite the wire length, the
general rule for AC stability required is C
C
8nF and R
C
1k
.
(4)
Method 2
The compensation network in Figure 2b is similar to the
circuitry used in method 1 but with an additional gate re-
sistor R
G
. The R
G
resistor helps to minimize high frequency
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