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參數(shù)資料
| 型號： | LTC4210-3IS6 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6 |
| 封裝： | PLASTIC, MO-193, TSOT-23, 6 PIN |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 216K |
| 代理商： | LTC4210-3IS6 |
10
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
WU
UU
power-up or during current limiting. The first type of oscil-
lation occurs at high frequencies, typically above 1MHz.
This high frequency oscillation is easily damped with RG as
mentioned in method 2.
The second type of oscillation occurs at frequencies
between 200kHz and 800kHz due to the load capacitance
being between 0.2
F and 9F, the presence of RG and RC
resistance, the absence of a drain bypass capacitor, a
combination of bus wiring inductance and bus supply output
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load
capacitance below 10
F, the second choice is connect-
ing an external CP > 1.5nF.
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance CGATE also
determines the GATE start-up as in Equation 6. The CGATE
should be kept below 0.15
F at high supply operation as
the capacitive energy ( 0.5 CGATE VGATE2 ) is discharged
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is serving during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, CTIMER. There are two comparator
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5
A pull-up
60
A pull-up
2
A pull-down
100
A pull-down
The 100
Aisanonidealcurrentsourceapproximatinga7k
resistor below 0.4V.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply VIN at time
point 1 of Figure 3. The LTC4210 is in reset mode as the ON
pin is low. GATE is pulled low and the TIMER pin is pulled
low with a 100
A source. At time point 2, the short pin
makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5
A. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
ends. The 100
A current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
CTIMER by equation:
tINITIAL ≈ 272.9 CTIMER ms/F
(5)
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
Start-Up Cycle Without Current Limit
The GATE is released with a 10
A pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold VTH and VOUT starts to follow the
1
>2.5V
COMP2
100
A
10
A
VIN
VON
VGATE
RESET
MODE
VOUT
VTIMER
23 4 5
6
7
COMP1
4210 F03
5
A
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
DISCHARGE
BY LOAD
VTH
>1.3V
Figure 3. Normal Operating Sequence
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