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參數(shù)資料
| 型號： | LTC4219IDHC-5#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | 5 X 3 MM, LEAD FREE, PLASTIC, MO-229WJED-1, DFN-16 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 195K |
| 代理商： | LTC4219IDHC-5#TRPBF |
LTC4219
11
4219fb
APPLICATIONS INFORMATION
versus time (Figure 2). The voltage at the GATE pin rises
with a slope of 0.3V/ms and the supply inrush current is
set at:
IINRUSH = CL (0.3V/ms)
This gate slope is designed to charge up a 1000μF capacitor
to 12V in 40ms, with an inrush current of 300mA. This
allows the inrush current to stay under the current limit
threshold (1.5A) for capacitors less than 1000μF. Included
in the Typical Performance Characteristics section is a
graph of the Safe Operating Area for the MOSFET. It is
evident from this graph that the power dissipation at 12V,
300mA for 40ms is in the safe region.
Figure 2. Supply Turn-On
Figure 1. 2A, 12V Card Resident Application
The typical LTC4219 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. A complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
Turn-On Sequence
Several conditions must be present before the internal
pass MOSFET can be turned on. First the supply VDD must
exceed its undervoltage lockout level. Next the internally
generated supply INTVCC must cross its 2.65V under-
voltage threshold. This generates a 25μs power-on-reset
pulse which clears the fault register and initializes internal
latches. Finally, the enable inputs EN1 and EN2 both must
be below the 1.15V threshold. All of these conditions must
be satised for the duration of 100ms to ensure that any
contact bounce during the insertion has ended.
The MOSFET is turned on by charging up the GATE with
a charge pump generated current source whose value is
adjusted by shunting a portion of the pull-up current to
ground. The charging current is controlled by the INRUSH
circuit that maintains a constant slope of GATE voltage
t1
t2
SLOPE = 0.3V/ms
GATE
OUT
VDD + 6.15
VDD
4219 F02
ADC
C1
0.1μF
12V
4219 F01
R4
10k
12V
R1
10k
CT
0.1μF
CL
330μF
VOUT
12V
2A
VDD
EN1
OUT
PG
GND
IMON
RSET
20k
RMON
20k
ISET
CGATE
0.1μF
RGATE
1k
GATE
LTC4219DHC-12
EN2
INTVCC
TIMER
FLT
+
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| LTC4219IDHC-12#TRPBF | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
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| LTC4219CDHC-5#PBF | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
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