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參數(shù)資料
| 型號(hào)： | LTC4224CDDB-2#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | LTC4224CDDB-2#TRPBF |
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LTC4224-1/LTC4224-2
7
422412fa
APPLICATIONS INFORMATION
VCC Selection
The LTC4224 is powered from the higher of its two supply
pins, VCC1 and VCC2.This allows the part to control a sup-
ply voltage as low as 1V, while the other supply is 2.7V or
greater. If both supplies are tied together, the part derives
its power from both equally. The Functional Diagram shows
the VCC selection circuit in an ideal diode OR-ing arrange-
ment. It is designed to ensure swift and smooth internal
power switchover from one supply to the other.
Turn-On Sequence
Separate ON1 and ON2 pins allow the VCC1 and VCC2
supplies to be turned on in any order. The power supplies
delivered to a plug-in card are controlled by external N-
channel MOSFETs, Q1 and Q2. For X2/XENPAK dened
optical transceiver modules, it has been specied that the
MOD DETECT pin pulls low inside the module through a
1k resistor (RMOD_DET), as shown in Figure 1. Several
conditions must be satised to turn on the MOSFETs.
First, VCC1 or VCC2 must exceed the 2.4V VCC undervoltage
lockout level for longer than an internal UV turn-on delay
of 160ms. Next, if VCCn is greater than 0.8V and ONn is
low (<0.8V), a debounce delay of 10ms is started. If VCCn
drops below 0.8V or ONn goes high before the end of the
10ms debounce delay, the debounce delay is restarted the
next time these pins are properly conditioned.
When the 10ms debounce delay expires, the external
MOSFET is turned on by charging up the GATE with a
Figure 2. Normal Power-Up Sequence
VOUT1
5V/DIV
VOUT2
5V/DIV
5ms/DIV
422412 F02
ON1/2
2V/DIV
GATE1
5V/DIV
GATE2
5V/DIV
10μA charge pump generated current source. When the
GATE voltage reaches the MOSFET threshold voltage, the
inrush current can build up quickly as the GATE continues
to rise. The ACL amplier actively controls the gate volt-
age to maintain 25mV across the sense resistor. In this
condition, the inrush current is given by:
IINRUSH =
25mV
RSENSE
As the inrush current charges up the load capacitor, the
output rises with a corresponding increase in gate voltage.
When the supply is no longer in current limit, an internal
charge pump pulls the gate to 5.5V above the higher of VCC1
or VCC2 to achieve a low resistance power path. Figure 2
shows a typical start-up sequence with CLOAD1 = CLOAD2
= 150μF, RLOAD1 = 4.7Ω and RLOAD2 = 2Ω.
The inrush current can be reduced to below the current
limit level by adding an external gate capacitor as shown
in Figure 3.
GATE capacitor CGATEprovidesgateslewratecontroltolimit
the inrush current. However, CGATE could cause parasitic
high frequency self oscillation in Q1. A 10Ω resistor, RG, as
shown in Figure 3 can be used to prevent the oscillation.
To be effective, RG needs to be laid out close to Q1.
The voltage at the GATE pin rises with a slope equal to IGATE/
CGATE. For a given supply inrush current IINRUSH and load
capacitor CLOAD, CGATE can be calculated according to:
CGATE =
IGATE
IINRUSH
CLOAD
Figure 3. Inrush Current Control by Gate Capacitor
422412 F03
LTC4224
VCC1 SENSE1
GATE1
R1
0.015Ω
5V
IGATE
CGATE
RG
10Ω
CLOAD
Q1
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| LTC4224IDDB-2#TRPBF | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
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| LTC4224CDDB-1#PBF | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
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