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參數資料
| 型號： | LTC4224IDDB-1#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件頁數： | 3/16頁 |
| 文件大?。?/td> | 215K |
| 代理商： | LTC4224IDDB-1#PBF |
LTC4224-1/LTC4224-2
11
422412fa
APPLICATIONS INFORMATION
Figure 11. Recommended Layout for Input
Supply Transient Protection Network
422412 F11
RSNUB
CSNUB
LTC4224
1
VCC2
GATE2
GND
2
SENSE2
3
4
5
10
9
8
7
6
Z1
VCC2
SNUBBER
NETWORK
VIAS TO
GND PLANE
PCB layout for the sense resistors and the power MOSFETs
should include good thermal management techniques for
optimal device power dissipation. A recommended PCB
layout for the sense resistors and the power MOSFET
around the LTC4224 is illustrated in Figure 12. Note that
it is important to keep the trace from the LTC4224’s GATE
pin to the FDS6911’s gate short.
In Hot Swap applications where load currents can be 10A,
wide PCB traces are recommended to minimize resistance
and temperature rise. The suggested trace width for 1oz
copper foil is 0.03" for each ampere of DC current to keep
PCB trace resistance, voltage drop and temperature rise to
a minimum. Note that the sheet resistance of 1oz copper
foil is approximately 0.5mΩ/square and voltage drops
due to trace resistances add up quickly in high current
applications.
In most applications, it is necessary to use plated-through
vias to make circuit connections from component layers to
power and ground layers internal to the PCB. For 1oz cop-
per foil plating, a general rule is 1A of DC current per via.
Consult your PCB fabrication facility for design rules
pertaining to other plating thicknesses.
Design Example
As a design example, consider the following specications:
VCC1 = 5V, VCC2 = 3.3V, ILOAD1(MAX) = 1A, ILOAD2(MAX) = 2A,
CLOAD1 = CLOAD2 = 150μF (see Figure 1).
First, select the sense resistor for each supply. Calculate
the R1 and R2 values based on the maximum load cur-
rent and the minimum circuit breaker threshold limit,
ΔVSENSE(CB)(MIN).
If a 1% tolerance is assumed for the sense resistors, then
the following values of resistance should sufce:
Table 2. Sense Resistor Values
SUPPLY VOLTAGE
RSENSE (1%)
ITRIP(MIN)
ITRIP(MAX)
5V
15mΩ
1.49A
1.85A
3.3V
10mΩ
2.23A
2.78A
For proper operation, ITRIP(MIN) must exceed the maxi-
mum load current with margin, so RSENSE1 = 15mΩ and
RSENSE2 = 10mΩ should sufce for the VCC1 and VCC2
supplies respectively.
Figure 12. Recommended Layout for
Power MOSFET and Sense Resistors
422412 F12
TOP SIDE
FDS6911
BOTTOM SIDE
LTC4224
11
6
8
7
9
10
5
4
2
3
1
5
6
4
3
7
8
2
1
5V
3.3V
R2
R1
Also, bypass locally with a 10μF electrolytic and 100nF
ceramic, or alternatively clamp the input with a transient
voltage suppressor (Z1) as shown in Figure 10. A 10Ω,
100nF snubber damps the response and eliminates ring-
ing. A recommended layout of the transient protection
devices Z1, RSNUB and CSNUB around the LTC4224 is
shown in Figure 11.
PCB Layout Considerations
For proper operation of the LTC4224’s electronic circuit
breaker, Kelvin connections to the sense resistors are
strongly recommended. The PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition, the
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