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參數(shù)資料
| 型號： | LTC4258CGW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POE 802.3AF QUAD 36-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 3 V ~ 4 V |
| 電流 - 電源： | 2.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
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LTC4258
8
4258fb
DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4258
Powered Device (PD) detection and classification hard-
ware monitors port 1 with this pin. Connect DETECT1 to
the output port via a low leakage diode (see Figure 1). If the
port is unused, the DETECT1 pin can be tied to AGND or
allowed to float.
DETECT2 (Pin 12): Detection Sense, Port 2. See DETECT1.
DETECT3 (Pin 13): Detection Sense, Port 3. See DETECT1.
DETECT4 (Pin 14): Detection Sense, Port 4. See DETECT1.
DGND (Pin 15): Digital Ground. DGND should be con-
nected to the return from the 3.3V supply. DGND and
AGND should be tied together.
VDD (Pin 16): Logic Power Supply. Connect to a 3.3V
power supply relative to DGND. VDD must be bypassed to
DGND near the LTC4258 with at least a 0.1
F capacitor.
SHDN1 (Pin 17): Shutdown Port 1, Active Low. When
pulled low, SHDN1 shuts down port 1, regardless of the
state of the internal registers. Pulling SHDN1 low is
equivalent to setting the Reset Port 1 bit in the Reset
Pushbutton register (1Ah). Internal filtering of the SHDN1
pin prevents glitches less than 1
s wide from reseting the
LTC4258. Pull SHDN1 high with
≤10k or tie to VDD.
SHDN2 (Pin 18): Shutdown Port 2, Active Low. See
SHDN1.
SHDN3 (Pin 19): Shutdown Port 3, Active Low. See
SHDN1.
SHDN4 (Pin 20): Shutdown Port 4, Active Low. See
SHDN1.
AGND (Pin 21): Analog Ground. AGND should be con-
nected to the return from the – 48V supply. AGND and
DGND should be tied together.
SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4
monitors the external MOSFET current via a 0.5
sense
resistor between SENSE4 and VEE. Whenever the voltage
across the sense resistor exceeds the overcurrent detec-
tion threshold VCUT, the current limit fault timer counts up.
If the voltage across the sense resistor reaches the current
limit threshold VLIM (typically 25mV/50mA higher), the
GATE4 pin voltage is lowered to maintain constant current
in the external MOSFET. See Applications Information for
further details. If the port is unused, the SENSE4 pin must
be tied to VEE.
GATE4 (Pin 23): Port 4 Gate Drive. GATE4 should be
connected to the gate of the external MOSFET for port 4.
When the MOSFET is turned on, a 50
A pull-up current
source is connected to the pin. The gate voltage is clamped
to 13V (typ) above VEE. During a current limit condition,
the voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down with 50
A, turning the
MOSFET off and recording a tICUT or tSTART event. If the
port is unused, float the GATE4 pin or tie it to VEE.
OUT4 (Pin 24): Port 4 Output Voltage Monitor. OUT4
should be connected to the output port through a 10k
series resistor. A current limit foldback circuit limits the
power dissipation in the external MOSFET by reducing the
current limit threshold when the port voltage is within 18V
of AGND. The port 4 Power Good bit is set when the voltage
from OUT4 to VEE drops below 2V (typ). A 2.5M resistor
is connected internally from OUT4 to AGND. If the port is
unused, the OUT4 pin can be tied to AGND or allowed to
float.
SENSE3 (Pin 25): Port 3 Current Sense Input. See SENSE4.
GATE3 (Pin 26): Port 3 Gate Drive. See GATE4.
OUT3 (Pin 27): Port 3 Output Voltage Monitor. See OUT4.
VEE (Pin 28): – 48V Supply Input. Connect to a – 48V to
– 57V supply, relative to AGND.
SENSE2 (Pin 29): Port 2 Current Sense Input. See SENSE4.
GATE2 (Pin 30): Port 2 Gate Drive. See GATE4.
OUT2 (Pin 31): Port 2 Output Voltage Monitor. See OUT4.
SENSE1 (Pin 32): Port 1 Current Sense Input. See SENSE4.
GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4.
OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4.
AUTO (Pin 35): Auto Mode Input. Auto mode allows the
LTC4258 to detect and power up a PD even if there is no
host controller present on the I2C bus. The voltage of the
AUTO pin determines the state of the internal registers
when the LTC4258 is reset or comes out of VDD UVLO (see
the Register map in Table 1). The states of these register
bits can subsequently be changed via the I2C interface.
The real-time state of the AUTO pin is read at bit 0 in the
Pin Status register (11h). Pull AUTO high or low with
≤10k
or tie to VDD or DGND.
NC (Pin 36): No Internal Connection.
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