參數(shù)資料
型號(hào)： LTC4259ACGW
廠商： Linear Technology
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC CTRLR POE QUAD AC DISC 36SSOP
標(biāo)準(zhǔn)包裝： 32
控制器類(lèi)型： 以太網(wǎng)供電控制器（POE）
接口： I²C
電源電壓： 3 V ~ 4 V
電流 - 電源： 2.5mA
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 36-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
LTC4259A
23
4259afb
OSCIN Input and Oscillator Requirements
AC disconnect depends on an external oscillator source
applied to the OSCIN pin. The LTC4259A measures port
impedance by applying an amplified version of the OSCIN
signal to the port’s DETECT pin (see Figure 18). The
oscillator should be well-controlled because errors in this
signal become errors in the measured port impedance. As
shown in Figure 19, the load being sensed by AC discon-
nect has a resistive and a large reactive component.
Current through the PD’s signature resistor depends on
the amplitude of the AC signal while current into the
capacitors depends on the slew rated: I = C dV/dt.
Consequently, the LTC4259A is sensitive to the amplitude
and slew rate of the OSCIN signal, but is more tolerant of
frequency and offset errors. Internal limits prevent the
LTC4259A from being adversely affected by OSCIN sig-
nals with excessive amplitude.
There are many ways to build oscillators with controlled
amplitudes and slew rates, especially since the frequency
of the oscillator does not have to be well-controlled.
Contact the LTC Applications department for oscillator
circuits.
As alluded to previously, AC disconnect is complicated
and redesigning for different component sizes is a difficult
task. For optimum performance, use the recommended
component values and drive OSCIN with a 100Hz 2VP-P,
1.2V offset sine wave. Keep in mind that the IEEE 802.3af
specification places upper limits of 100V/ms on the slew
rate and 500Hz on the frequency of the AC signal at the
port. Voltage gain, AVACD, from OSCIN to DETECTn in-
creases the slew rate by the voltage gain. Since AVACD has
a maximum absolute value of 3.3V/V (
±3V typ), the slew
rate at the OSCIN pin must be less than 30V/ms. A slew
rate around 0.6V/ms at OSCIN will work with the recom-
mended values of CDET, RDET and CPSE.
The LTC4259A’s OSCIN input amplifier will accept signals
between DGND – 0.3V and VDD + 0.5V. This amplifier has
a gain of –1 and is referenced to 1.2V above DGND. An
OSCIN voltage greater than 2.2V will cause the amplifier’s
output to clip against DGND. Clipping will not affect the
performance of AC disconnect until the clipping becomes
so severe that even the midrange (where the controlled
slew rate occurs) of the signal is clipped. Keep the midrange
or average voltage of the OSCIN signal between 0.9V and
1.5V to avoid severe clipping. OSCIN signals below DGND
can interact with the ESD protection circuitry on the pin
and are not recommended. Also, meeting the IEEE 802.3af
specification for maximum AC amplitude on the port just
after the PD is removed depends on the OSCIN input peak-
to-peak amplitude. Clipping by LTC4259A’s OSCIN input
circuitry will generally ensure that this specification is not
exceeded. Note that under normal operation, the AC dis-
connect output on the DETECT
n pin will have an amplitude
near 6V peak-to-peak. The combination of RDET, CDET and
CPSE attenuate the signal so roughly half this amplitude is
seen at the port when the port is powered and the PD has
just been removed. When the PD is still connected there
will be almost no AC signal at the port.
The LTC4259A monitors Pin 36 for the presence of an
oscillating signal. If no signal is present and the Osc Fail
Mask bit is set, then Osc Fail (bit 1 of the Supply Event
register) is set, triggering an interrupt. As the LTC4259A’s
AC disconnect circuitry self-checks the OSCIN signal, the
Osc Fail bit is intended as a fault indicator to alert the PSE
host controller. The Osc Fail bit has no effect beyond
triggering the interrupt. A clear Osc Fail bit indicates that
the OSCIN signal goes below 0.6V and above 1.8V at least
once every 250ms. It does not necessarily guarantee that
AC disconnect will function properly. However, AC discon-
nect itself is a more thorough test of the OSCIN signal.
When the OSCIN signal is either absent or corrupted,
powered ports with AC disconnect enabled (and DC dis-
connect not enabled) will automatically disconnect. After
the LTC4259A is reset (by power on, Reset All bit or the
RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is
cleared, it will only be set by an invalid signal on the OSCIN
pin or another reset.
SERIAL DIGITAL INTERFACE
The LTC4259A communicates with a host (master) using
the standard 2-wire interface as described in the SMBus
Specification Version 2.0 (available at http://smbus.org).
The SMBus is an extension of the I2C bus, and the
LTC4259A is also compatible with the I2C bus standard.
The Timing Diagrams (Figures 6 through 10) show the
timing relationship of the signals on the bus. The two bus
APPLICATIO S I FOR ATIO
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