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參數(shù)資料
| 型號： | LTC6253CTS8#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP R-R 720MHZ TSOT23-8 |
| 標準包裝： | 1 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 280 V/µs |
| 增益帶寬積： | 720MHz |
| -3db帶寬： | 400MHz |
| 電流 - 輸入偏壓： | 1.4µA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 4.25mA |
| 電流 - 輸出 / 通道： | 100mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.25 V，±1.25 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 標準包裝 |
| 其它名稱： | LTC6253CTS8#TRMPBFDKR |
LTC6252/LTC6253/LTC6254
15
625234fc
APPLICATIONS INFORMATION
Figure 2. 5pF Feedback Cancels Parasitic Pole
Feedback Components
When feedback resistors are used to set up gain, care
must be taken to ensure that the pole formed by the
feedback resistors and the parasitic capacitance at the
inverting input does not degrade stability. For example
if the amplifier is set up in a gain of +2 configuration
with gain and feedback resistors of 5k, a parasitic ca-
pacitance of 5pF (device + PC board) at the amplifier’s
inverting input will cause the part to oscillate, due to
a pole formed at 12.7MHz. An additional capacitor of
5pF across the feedback resistor as shown in Figure 2
will eliminate any ringing or oscillation. In general, if
the resistive feedback network results in a pole whose
frequency lies within the closed loop bandwidth of the
amplifier, a capacitor can be added in parallel with the
feedback resistor to introduce a zero whose frequency
is close to the frequency of the pole, improving stability.
624678 F02
CPAR
5k
–
+
VOUT
VIN
5k
5pF
Power Dissipation
The LTC6252 and LTC6253 contain one and two amplifiers
respectively. Hence the maximum on-chip power dissipa-
tion for them will be less than the maximum on-chip power
dissipationfortheLTC6254,whichcontainsfouramplifiers.
The LTC6254 is housed in a small 16-lead MS package and
typically has a thermal resistance (
qJA) of 125°C/ W. It is
necessary to ensure that the die’s junction temperature
does not exceed 150°C. The junction temperature, TJ, is
calculated from the ambient temperature, TA, power dis-
sipation, PD, and thermal resistance,
qJA:
TJ = TA + (PD qJA)
The power dissipation in the IC is a function of the supply
voltage, output voltage and load resistance. For a given
supply voltage with output connected to ground or supply,
the worst-case power dissipation PD(MAX) occurs when
the supply current is maximum and the output voltage at
half of either supply voltage for a given load resistance.
PD(MAX) is approximately (since IS actually changes with
output load current) given by:
PD(MAX) =(VS IS(MAX))+
VS
2
2
/ RL
Example:ForanLTC6254ina16-leadMSpackageoperating
on ±2.5V supplies and driving a 100Ω load to ground, the
worst-case power dissipation is approximately given by
PD(MAX)/Amp = (5 4.8mA) + (1.25)2/100 = 39.6mW
If all four amplifiers are loaded simultaneously then the
total power dissipation is 158mW.
AttheAbsoluteMaximumambientoperatingtemperature,
the junction temperature under these conditions will be:
TJ = TA + PD 125°C/W
= 125 + (0.158W 125°C/W) = 145°C
which is less than the absolute maximum junction tem-
perature for the LTC6254 (150°C).
Refer to the Pin Configuration section for thermal resis-
tances of various packages.
Shutdown
The LTC6252 and LTC6253MS have SHDN pins that can
shutdowntheamplifierto42Atypicalsupplycurrent.The
SHDN pin needs to be taken within 0.8V of the negative
supply for the amplifier to shut down. When left floating,
the SHDN pin is internally pulled up to the positive supply
and the amplifier remains on.
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