參數資料
| 型號： | LTC6253IDC#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 6/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP R-R 720MHZ DFN-8 |
| 標準包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 280 V/µs |
| 增益帶寬積： | 720MHz |
| -3db帶寬： | 400MHz |
| 電流 - 輸入偏壓： | 1.4µA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 4.25mA |
| 電流 - 輸出 / 通道： | 100mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.25 V，±1.25 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 8-DFN-EP（2x2） |
| 包裝： | 帶卷 (TR) |
LTC6252/LTC6253/LTC6254
14
625234fc
APPLICATIONS INFORMATION
Input Offset Voltage
The offset voltage will change depending upon which
input stage is active. The PNP input stage is active from
the negative supply rail to approximately 1.2V below the
positive supply rail, then the NPN input stage is activated
for the remaining input range up to the positive supply rail
with the PNP stage inactive. The offset voltage magnitude
for the PNP input stage is trimmed to less than 350V with
5V total supply at room temperature, and is typically less
than 150μV. The offset voltage for the NPN input stage is
less than 2.2mV with 5V total supply at room temperature.
Input Bias Current
The LTC6252 family uses a bias current cancellation cir-
cuit to compensate for the base current of the PNP input
pair. This results in a typical IB of about 100nA. When the
input common mode voltage is less than 200mV, the bias
cancellation circuit is no longer effective and the input
bias current magnitude can reach a value above 4A. For
common mode voltages ranging from 0.2V above the
negative supply to 1.2V below the positive supply, the
low input bias current allows the amplifiers to be used in
applications with high source resistances where errors
due to voltage drops must be minimized.
Output
The LTC6252 family has excellent output drive capability.
The amplifiers can typically deliver 90mA of output drive
current at a total supply of 5V. The maximum output
current is a function of the total supply voltage. As the
supply voltage to the amplifier decreases, the output
current capability also decreases. Attention must be paid
to keep the junction temperature of the IC below 150°C
(refer to the Power Dissipation Section) when the output
is in continuous short-circuit. The output of the amplifier
has reverse-biased diodes connected to each supply. If
the output is forced beyond either supply, extremely high
current will flow through these diodes which can result
in damage to the device. Forcing the output to even 1V
beyond either supply could result in several hundred mil-
liamps of current through either diode.
Input Protection
TheLTC6252/LTC6253/LTC6254inputstagesareprotected
against a large differential input voltage of 1.4V or higher
by 2 pairs of back-to-back diodes to prevent the emitter-
base breakdown of the input transistors. In addition, the
input and shutdown pins have reverse biased diodes con-
nected to the supplies. The current in these diodes must
be limited to less than 10mA. The amplifiers should not be
used as comparators or in other open loop applications.
ESD
The LTC6252 family has reverse-biased ESD protection
diodes on all inputs and outputs as shown in Figure 1.
There is an additional clamp between the positive and
negative supplies that further protects the device during
ESD strikes. Hot plugging of the device into a powered
socket must be avoided since this can trigger the clamp
resultinginlargercurrentsflowingbetweenthesupplypins.
Capacitive Loads
The LTC6252/LTC6253/LTC6254 are optimized for high
bandwidthandlowpowerapplications.Consequentlythey
have not been designed to directly drive large capacitive
loads. Increased capacitance at the output creates an ad-
ditional pole in the open loop frequency response, wors-
ening the phase margin. When driving capacitive loads, a
resistor of 10Ω to 100Ω should be connected between the
amplifier output and the capacitive load to avoid ringing
or oscillation. The feedback should be taken directly from
the amplifier output. Higher voltage gain configurations
tend to have better capacitive drive capability than lower
gain configurations due to lower closed loop bandwidth
and hence higher phase margin. The graphs titled Series
Output Resistor vs Capacitive Load demonstrate the tran-
sient response of the amplifier when driving capacitive
loads with various series resistors.
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