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參數(shù)資料
| 型號： | LTC6360CMS8E#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DRIVER TRUE ZERO 8-MSOP |
| 標準包裝： | 50 |
| 類型： | ADC 驅(qū)動器 |
| 應用： | 數(shù)據(jù)采集 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）裸露焊盤 |
| 供應商設備封裝： | 8-MSOP-EP |
| 包裝： | 管件 |
LTC6360
15
6360f
applicaTions inForMaTion
The amount that the loop gain and subsequent bandwidth
willbereducedisequaltothiszero-poleratio.Forexample,
for 20dB of loop gain reduction (one decade bandwidth
reduction), RFILT should be made equal to 5Ω.
Figure 8 shows the open loop gain without compensation
and with a 10Ω/330pF RC compensation network. The
pole-zero can be seen to reduce the open loop gain above
10MHz,stabilizingtheamplifierforunitygainapplications.
This sets a lower limit on CL of:
CFILT > (fZ / fP NG)/(2πRFILTfC(AMP))
(8)
Note that for large zero-pole ratios, additional margin
may be needed. In this case, setting fZ equal to fC yields
a phase margin of at best 45°. In practice, the ampli-
fier’s higher order poles will further reduce the phase
margin below 45°. Therefore, fZ should be made lower
thanfCinordertoensureadequatephasemargin.Phase
margin in the case of large pole-zero ratios case can
be estimated as tan–1(fC/fZ).
Likewise for small zero-pole ratios, the pole will not
have contributed a full 90° of lagging phase prior to the
zero contributing leading phase. The requirement for
fZ being lower than fC can be relaxed in these cases.
3. SelectRFILTandCFILTtoyieldthedesiredfilterbandwidth
while meeting the two constraints listed above.
The layout of the filter RC network is critical to the stability
of the part and care should be taken to minimize parasitic
inductance in this path.
Table 1 lists suggested RC filter values for some common
circuit gains. Note that longer filter time constants can be
implemented by increasing the CFILT value beyond what is
showninTable1withoutdegradingstability.ForlargeCFILT
values, it may be necessary to use multiple high quality
surface mount capacitors to reduce ESR and maintain a
high self resonant frequency.
Table 1. Component Values for Various Circuit Gains
Noise Gain (NG)
RF
CF
RG
RFILT
CFILT
1
0
DNI
10
330pF
2
2k
2pF
2k
25
150pF
5
2k
0.2pF
500
DNI
10
2k
DNI
222
DNI
20
2k
DNI
181
DNI
DNI – Do Not Install
Interfacing the LTC6360 to A/D Converters
When driving an ADC, a single-pole RC filter between
the output of the LTC6360 and the input of the ADC can
improve system performance. The sampling process
of ADCs creates a charge transient at the ADC input
The following is a guideline for designing the RC filter to
ensure stability with a circuit gain less than five:
1. In order to sufficiently reduce the gain prior to the
unity loop gain crossover point, fC, the zero-pole ratio
should be greater than 5/NG, where NG is the circuit
noise gain. For example, based on Equation 5, a unity
gain configuration allows a maximum RFILT value of
11.25Ω.
2. The zero should be located below to the unity gain
crossover frequency, fC. Once the RC network is in-
troduced, fC will occur at a lower frequency given by:
fC = fC(AMP)/(fZ / fP NG)
(6)
wherefC(AMP)istheunitygain-bandwidthoftheamplifier
without the RC network. Thus, the following condition
should be met:
fZ < fC(AMP)/(fZ / fP NG)
(7)
where fC(AMP) is approximately 1GHz.
Figure 8. Open Loop Gain and Phase with and without
Output Compensation
FREQUENCY (Hz)
10
1k 10k 100k 1M 10M 100M
GAIN
(dB)
PHASE
(DEG)
100
1G
6360 F08
120
100
–20
140
80
60
40
20
0
135
90
–180
180
45
0
–45
–90
–135
PHASE
UNCOMPENSATED
10/330pF
COMPENSATED
10/330pF
COMPENSATED
GAIN
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