minimized by matching the parallel im" />
參數(shù)資料
型號(hào): LTC6360IMS8E#PBF
廠商: Linear Technology
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: IC ADC DRIVER TRUE ZERO 8MSOP
標(biāo)準(zhǔn)包裝: 50
類型: ADC 驅(qū)動(dòng)器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 8-MSOP-EP
包裝: 管件
LTC6360
13
6360f
applicaTions inForMaTion
Input bias current induced DC voltage offsets can be
minimized by matching the parallel impedance of RF and
RG to the source impedance, RS. For example, in the
typical application when the amplifier is configured as a
unity gain buffer, choosing RF equal to RS will minimize
the offset. Since nonzero values of RFwillcontributetothe
total output noise, RF may be bypassed with a capacitor
to reduce the noise bandwidth.
Input Protection
Back-to-back diodes (D1 and D2 in Figure 5) are included
between +IN and –IN to protect the input devices. The
inputs do not have internal resistors in series with the
input transistors, a technique often used to protect the
input transistors from excessive current flow during an
overdrive condition. Adding series input resistors would
significantlydegradethelownoiseperformance.Therefore,
if the voltage across the amplifier’s inputs is allowed to
exceed ±0.7V, steady state current conducted through the
protection diodes should be externally limited to ±10mA.
The input diodes are rugged enough to handle transient
currentsduetoamplifierslewrateoverdriveormomentary
clipping without protection resistors.
Driving the input signal sufficiently beyond the specified
input common mode voltage range will cause the input
transistorstosaturate.Whensaturationoccurs,theampli-
fier loses a stage of phase inversion and the output will
begin to invert. Diode D1 or D2 (Figure 5) forward biases
andholdstheoutputwithinadiodedropoftheinputsignal.
To avoid this inversion, limit the input drive to within the
specified input common mode range.
ESD
The LTC6360 has ESD protection diodes on all inputs
and outputs. The diodes are reverse biased during nor-
mal operation. If the input pins are driven beyond either
supply, large currents will flow through these diodes. If
the current is transient and limited to 10mA or less, no
damage to the device will occur.
On-Chip Charge Pump
A low noise on-chip charge pump generates a small nega-
tive voltage that is used to bias the output stage of the
amplifier, enabling output swing below 0V. The charge
pump output voltage is typically –0.6V. Several design
techniques have been used to lower the ripple present
at OUT due to the switching action of the charge pump.
The charge pump output is made available via the CPO
pin, and the amplifier’s charge pump input at the CPI pin.
This allows additional external filtering via a capacitor
connected from CPI to GND.
The charge pump operates at a nominal frequency of
10MHz.TheoutputvoltageatCPOwillhavesmallfrequency
components at multiples of 5MHz. These components
are further reduced by the PSRR of the amplifier’s out-
put stage. The amplitude of the fundamental component
at the OUT pin is typically 1VRMS with a 0.1F bypass
capacitor at CPI.
Conventionally, a two chip solution is chosen to provide
output swing to true zero on a single supply: one ampli-
fier and an inverting charge pump to provide a negative
rail. Compared to a two chip solution, the LTC6360 offers
several advantages: a more compact layout with lower
part count, lower output ripple, less EMI and lower power.
Figure 6 shows the ripple voltage spectrum at the output,
VOUT, with a 0.1F external CPI bypass capacitor.
Figure 6. Output Ripple Voltage
FREQUENCY (MHz)
V OUT
(V
RMS
)
1
0.1
10
100
80
60
40
20
0
6360 F06
INPUT GROUNDED
0.1F CPI BYPASS CAPACITOR
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