AIN+
參數(shù)資料
型號: LTC6403CUD-1#TRPBF
廠商: Linear Technology
文件頁數(shù): 10/20頁
文件大小: 0K
描述: IC AMP/DRIVER LN LP 16-QFN
標準包裝: 2,500
類型: ADC 驅(qū)動器
應用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應商設備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
LTC6403-1
18
64031fa
+
1
SHDN
5
6
–IN
7
+OUT
8
+OUTF
16
15
+IN
NC
14
–OUT
13
–OUTF
AIN+
AIN
402
Ω
2
V+
3
V
V+
V
3.3V
VOCM
12
V
11
V+
10
V+
9
V
64031 F11
LTC6403-1
LTC2207
VIN, 2VP-P
SHDN
402
Ω
402
Ω
402
Ω
0.1
μF
3.3V
4
0.1
μF
0.1
μF
CONTROL
GND
VDD
D15
D0
0.1
μF
VCM
2.2
μF
3.3V
1
μF
APPLICATIONS INFORMATION
Figure 11. Interfacing the LTC6403-1 to ADC (Shared 3.3V Supply Voltage)
Interfacing the LTC6403-1 to A/D Converters
The LTC6403-1’s rail-to-rail output and fast settling time
make the LTC6403-1 ideal for interfacing to low voltage,
single supply, differential input ADCs. The sampling process
of ADCs creates a sampling glitch caused by switching
in the sampling capacitor on the ADC front end which
momentarily shorts the output of the amplier as charge
is transferred between the amplier and the sampling
capacitor. The amplier must recover and settle from
this load transient before this acquisition period ends for
a valid representation of the input signal. In general, the
LTC6403-1 will settle much more quickly from these pe-
riodic load impulses than from a 2V input step, but it is
a good idea to either use the ltered outputs to drive the
ADC (Figure 11 shows an example of this), or to place a
discrete R-C lter network between the differential unl-
tered outputs of the LTC6403-1 and the input of the ADC
to help absorb the charge injection that comes out of the
ADC from the sampling process. The capacitance of the
lter network serves as a charge reservoir to provide high
frequency charging during the sampling process, while the
two resistors of the lter network are used to dampen and
attenuate any charge kickback from the ADC. The selection
of the R-C time constant is trial and error for a given ADC,
but the following guidelines are recommended: Choosing
too large of a resistor in the decoupling network will create
a voltage divider between the dynamic input impedance of
the ADC and the decoupling resistors leaving insufcient
settling time. Choosing too small of a resistor will possibly
prevent the resistor from properly dampening the load
transient caused by the sampling process, prolonging
the time required for settling. 16-bit applications require
a minimum of 11 R-C time constants to settle. It is rec-
ommended that the capacitor chosen have a high quality
dielectric (for example, C0G multilayer ceramic).
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