VS = 3V, RLOAD <" />
參數(shù)資料
型號(hào): LTC6403IUD-1#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 19/20頁(yè)
文件大?。?/td> 0K
描述: IC AMP/DRIVER LN LP 16-QFN
標(biāo)準(zhǔn)包裝: 2,500
類型: ADC 驅(qū)動(dòng)器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
LTC6403-1
8
64031fa
20ns/DIV
0.2V/DIV
64031 G23
VS = 3V, RLOAD = 800Ω
VIN = 2VP-P DIFFERENTIAL
–OUT
+OUT
50ns/DIV
VOLTAGE
(V)
2.0
2.5
3.0
64031 G24
1.5
1.0
0.5
0
–OUT
+OUT
VS = 3V
VOCM = 1.5V
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Step Response
Overdrive Transient Response
SHDN (Pin 1): When SHDN is oating or directly tied to V+,
the LTC6403-1 is in the normal (active) operating mode.
When Pin 1 is pulled a minimum of 2.1V below V+, the
LTC6403-1 enters into a low power shutdown state. See
Applications Information for more details.
V+, V(Pins 2, 10, 11 and Pins 3, 9, 12):
Power Supply
Pins. Three pairs of power supply pins are provided to keep
the power supply inductance as low as possible to prevent
any degradation of amplier 2nd harmonic performance. It
is critical that close attention be paid to supply bypassing.
For single supply applications (Pins 3, 9 and 12 grounded)
it is recommended that high quality 0.1μF surface mount
ceramic bypass capacitors be placed between Pins 2 and
3, between Pins 11 and 12, and between Pins 10 and 9
with direct short connections. Pins 3, 9 and 10 should be
tied directly to a low impedance ground plane with minimal
routing. For dual (split) power supplies, it is recommended
that at least two additional high quality, 0.1μF ceramic
capacitors are used to bypass pin V+ to ground and Vto
ground, again with minimal routing. For driving large loads
(<200
Ω),additionalbypasscapacitancemaybeneededfor
optimal performance. Keep in mind that small geometry
(e.g. 0603) surface mount ceramic capacitors have a much
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
PIN FUNCTIONS
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