參數(shù)資料
型號: LTC6404IUD-4#TRPBF
廠商: Linear Technology
文件頁數(shù): 20/28頁
文件大小: 0K
描述: IC AMP/DRIVER DIFF 16-QFN
標準包裝: 2,500
類型: ADC 驅(qū)動器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
LTC6404
27
6404f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm
× 3mm)
(Reference LTC DWG # 05-08-1691)
will create a voltage divider between the dynamic input
impedance of the ADC and the decoupling resistors.
Choosing too small of a resistor will possibly prevent the
resistor from properly damping the load transient caused
by the sampling process, prolonging the time required for
APPLICATIONS INFORMATION
settling. 16-bit applications typically require a minimum
of 11 R-C time constants. It is recommended that the ca-
pacitor chosen have a high quality dielectric (for example,
C0G multilayer ceramic).
3.00
± 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45
± 0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40
± 0.10
BOTTOM VIEW—EXPOSED PAD
1.45
± 0.10
(4-SIDES)
0.75
± 0.05
R = 0.115
TYP
0.25
± 0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25
× 45° CHAMFER
15
16
2
0.50 BSC
0.200 REF
2.10
± 0.05
3.50
± 0.05
0.70
±0.05
0.00 – 0.05
(UD16) QFN 0904
0.25
±0.05
0.50 BSC
PACKAGE OUTLINE
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