LTC6405
5
6405fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins (+IN, –IN, VOCM, SHDN and VTIP) are protected by
steering diodes to either supply. If the inputs should exceed either supply
voltage, the input current should be limited to less than 10mA. In addition,
the inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely.
Note 4: The LTC6405C/LTC6405I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6405C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6405C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6405I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: Input bias current is defined as the average of the input currents
flowing into the inputs (–IN, and +IN). Input Offset current is defined as
the difference between the input currents (IOS = IB+ – IB–).
Note 7: Input common mode range is tested using the test circuit of Figure
1 by taking 3 measurements of differential gain with a ±1VDC differential
output with VICM = 0V; VICM = 2.5V; VICM = 5V, verifying that the
differential gain has not deviated from the VICM = 2.5V case by more than
0.5%, and that the common mode offset (VOSCM) has not deviated from
the common mode offset at VICM = 2.5V by more than ±35mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the VOCM pin and testing at
both VOCM = 2.5V and at the Electrical Characteristics table limits to verify
that the common mode offset (VOSCM) has not deviated by more than
±20mV from the VOCM = 2.5V case.
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of
the change in the voltage at the VOCM pin to the change in differential
input referred voltage offset. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
the “Effects of Resistor Pair Mismatch” in the Applications Information
section of this data sheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9: Differential Power Supply Rejection (PSRR) is defined as the
ratio of the change in supply voltage to the change in differential input
referred voltage offset. Common mode power supply rejection (PSRRCM)
is defined as the ratio of the change in supply voltage to the change in the
common mode offset, VOUTCM – VOCM.
Note 10: Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 11: Because the LTC6405 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power can be very small in many applications. In
order to compare the LTC6405 with “RF style” amplifiers that require 50Ω
load, the output voltage swing is converted to dBm as if the outputs were
driving a 50Ω load. For example, 2VP-P output swing is equal to 10dBm
using this convention.
Note 12: Includes offset/drift induced by feedback resistors mismatch. See
the Applications Information section for more details.
Note 13: QFN package only—refer to datasheet curves for MSOP package
numbers.
electrical characteristics