參數(shù)資料
型號(hào): LTC6409HUDB#TRMPBF
廠商: Linear Technology
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: IC AMP/DRIVER DIFF GBW 10-QFN
標(biāo)準(zhǔn)包裝: 500
類型: ADC 驅(qū)動(dòng)器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 10-WQFN
供應(yīng)商設(shè)備封裝: 10-TQFN(3x2)
包裝: 帶卷 (TR)
LTC6409
17
6409fa
applicaTions inForMaTion
Board Layout and Bypass Capacitors
For single supply applications, it is recommended that
high quality 0.1F||1000pF ceramic bypass capacitors
be placed directly between each V+ pin and its closest
Vpin with short connections. The Vpins (including the
Exposed Pad) should be tied directly to a low impedance
ground plane with minimal routing.
For dual (split) power supplies, it is recommended that
additionalhighquality0.1F||1000pFceramiccapacitorsbe
used to bypass V+ pins to ground and Vpins to ground,
again with minimal routing.
For driving heavy differential loads (<200Ω), additional
bypass capacitance may be needed for optimal perfor-
mance. Keep in mind that small geometry (e.g., 0603)
surface mount ceramic capacitors have a much higher
self-resonant frequency than do leaded capacitors, and
perform best in high speed applications.
To prevent degradation in stability response, it is highly
recommended that any stray capacitance at the input
pins, +IN and –IN, be kept to an absolute minimum by
keeping printed circuit connections as short as possible.
This becomes especially true when the feedback resistor
network uses resistor values greater than 500Ω in circuits
with RI = RF.
At the output, always keep in mind the differential nature of
theLTC6409,becauseitiscriticalthattheloadimpedances
seen by both outputs (stray or intended), be as balanced
and symmetric as possible. This will help preserve the
balanced operation of the LTC6409 that minimizes the
generation of even-order harmonics and maximizes the
rejection of common mode signals and noise.
The VOCMpinshouldbebypassedtothegroundplanewith
a high quality ceramic capacitor of at least 0.01F. This
will prevent common mode signals and noise on this pin
from being inadvertently converted to differential signals
and noise by impedance mismatches both externally and
internally to the IC.
Driving ADCs
TheLTC6409’sground-referencedinput,differentialoutput
and adjustable output common mode voltage make it ideal
for interfacing to differential input ADCs. These ADCs are
typically supplied from a single-supply voltage and have
an optimal common mode input range near mid-supply.
TheLTC6409interfacestotheseADCsbyprovidingsingle-
ended to differential conversion and common mode level
shifting.
The sampling process of ADCs creates a transient that is
caused by the switching in of the ADC sampling capaci-
tor. This momentarily shorts the output of the amplifier
as charge is transferred between amplifier and sampling
capacitor. The amplifier must recover and settle from this
load transient before the acquisition period has ended, for
a valid representation of the input signal. The LTC6409 will
settle quickly from these periodic load impulses. The RC
network between the outputs of the driver and the inputs
of the ADC decouples the sampling transient of the ADC
(see Figure 11). The capacitance serves to provide the
bulk of the charge during the sampling process, while
the two resistors at the outputs of the LTC6409 are used
to dampen and attenuate any charge injected by the ADC.
The RC filter gives the additional benefit of band limiting
broadband output noise. Generally, longer time constants
improve SNR at the expense of settling time. The resistors
in the decoupling network should be at least 10Ω. These
resistors also serve to decouple the LTC6409 outputs
from load capacitance. Too large of a resistor will leave
insufficient settling time. Too small of a resistor will not
properlydampentheloadtransientofthesamplingprocess,
prolonging the time required for settling. In 16-bit applica-
tions, this will typically require a minimum of eleven RC
time constants. For lowest distortion, choose capacitors
with low dielectric absorption (such as a C0G multilayer
ceramic capacitor).
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