參數(shù)資料
型號(hào)： LTC6412IUF#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 0K
描述： IC VGA ANLG-CNTRL 31DB 24-QFN
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 可變?cè)鲆?br>
電路數(shù)： 1
輸出類型： 差分
-3db帶寬： 800MHz
電流 - 電源： 110mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
LTC6412
16
6412fa
APPLICATIONS INFORMATION
grounding and supply decoupling. Failure to provide low
impedance supply and ground at high frequencies can
cause oscillations and increased distortion.
Enable/Shutdown
Both the EN pin and SHDN pin are self-biased to VCCthrough
their respective 100k pull-up resistors, so the default
open-pin state is powered on with the output amplier
signal path disabled. Pulling the EN pin low completes
the signal path from the attenuator ladder through the
output amplier. The EN pin essentially provides a fast
muting function while the SHDN pin provides slower
power on/off function.
For applications requiring the SHDN function, it is
recommended that the output amplier signal path be
disabled with a high EN voltage before transitioning the
SHDN signal. When enabling the amplier, allow at least
5ms dwell time between the rising SHDN transition and the
falling EN transition to avoid non-monotonic output signal
behavior though the VGA. The opposite delay sequence
is recommended for the falling SHDN transition, but this
is less critical as the output signal amplitude will drop
abruptly regardless of the EN pin.
SHDN
EN
tDWELL
6412 AI01
Layout/Grounding
The high frequency performance of the LTC6412 requires
special attention to proper RF grounding, bias decoupling
and termination. The recommended PCB stack-up for a
4-layer board is shown below for 1oz copper clad FR-4
laminate with a relative dielectric constant,
εr = 4.2-4.5
at 1GHz.
METAL 1
METAL 2
METAL 3
METAL 4
RF SIGNAL
FR4 12-18 MILS
FR4 20-30 MILS
FR4 NOT CRITICAL
GROUND PLANE
POWER PLANE
GND AND LF SIGNAL
6412 AI02
The topside metal and silkscreen drawings for Test Circuit A
illustrate the recommended decoupling capacitor place-
ment, signal routing and grounding. Ground vias directly
beneaththeExposedPadarecritical;useasmanyaspossible.
Ground vias to the other ground pins are less critical.
ESD
The LTC6412 is protected with reverse-biased ESD diodes
on all I/O pins. If any I/O pin is forced one diode drop above
the positive supply or one diode drop below the negative
supply, then large currents may ow through the diodes.
No damage to the devices will occur if the current is kept
below 10 mA. The +OUT/–OUT pins have additional series
diodes to the positive supply and can sustain approximately
2V overshoot above the positive supply before conducting
appreciable currents.
Signal Compression Characteristics
The graph entitled, Input and Output P1dB, illustrates
an important characteristic of the LTC6412 VGA. At gain
settings above –5dB, the output amplier limits the linear
power handling capability, but at gain settings below
–5dB, the input attenuator ladder limits the linear power
handling capability. The linear input power limitations at
minimum gain do not affect the overall performance of
a signal chain if the preceding mixer or amplier stage
exhibits an OP1dB < 19dBm and an OIP3 < 50dBm.
Test Circuits
The fully-differential nature of the LTC6412 design requires
two test circuits to generate the performance information
presented in this data sheet.
Test Circuit A is DC1464A, a 2-port demonstration circuit
with input/output balun transformers to allow for direct
connection to a 2-port network analyzer or other single-
ended 50Ω test system. The balun transformers limit the
high and low frequency performance of the LTC6412 but
allow for simple and reasonably accurate measurements
from 70MHz to 380MHz. The gain control signal is supplied
to either of the VG turrets for DC control measurements
or through the VGAIN SMA connector for transient control
signal measurements. Clip leads to the gain control turrets
are susceptible to noise pickup and should be lowpass
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