V+, V– (Pins 14, 13):" />
參數(shù)資料
型號(hào)： LTC6601CUF-2#TRPBF
廠商： Linear Technology
文件頁數(shù)： 5/40頁
文件大小： 0K
描述： IC FILTER/ADC DVR LP LD 20-QFN
標(biāo)準(zhǔn)包裝： 2,500
頻率 - 截止或中心： 27MHz
濾波器數(shù)： 3
濾波器階數(shù)： 2nd
電源電壓： 2.7 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
LTC6601-2
13
66012f
V+, V– (Pins 14, 13): Power Supply Pins. It is critical that
close attention be paid to supply bypassing. For single
supply applications (Pin 13 grounded), it is recommended
that a high quality 0.1μF surface mount ceramic bypass
capacitor (X7R dielectric for instance) be placed between
Pins 14 and 13, with direct short connections. Pin 13
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it
is recommended that at least two additional high quality
0.1μF ceramic capacitors are used to bypass V+ to ground
and V– to ground, again with minimal routing. For driving
large loads (< 200Ω), additional bypass capacitance may
be added for optimal performance. Keep in mind that small
geometry (e.g., 0603) surface mount ceramic capacitors
have a much lower ESL than do leaded capacitors, and
perform best in high speed applications.
C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF
capacitor which feeds the amplier noninverting sum-
ming node. Typically, either oat or tie to OUT–. For best
performance, stray capacitance should be kept as low as
possible by keeping printed circuit connections as short
and direct as possible.If necessary, strip back the sur-
rounding ground plane away from these pins.
C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF
capacitor which feeds an inverting summing node. Typi-
cally, either oat or tie to OUT+. If either of these pins are
tied to a low impedance source other than OUT+, a re-
sistance of at least 25Ω should be placed in series. For
best performance, it is highly recommended that stray
capacitance be kept to as low as possible by keeping printed
circuit connections as short and direct as possible, and if
necessary, stripping back nearby surrounding reference
plane away from these pins.
Exposed Pad (Pin 21): Always tie the underlying Exposed
Pad to V– (Pin 13). If split supplies are used, do not tie
the pad to ground. Tie it to V–.
PIN FUNCTIONS (Refer to the Block Diagram)
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LTC6601IUF-1#PBF 功能描述:IC DRVR FILTER/ADC LN 20-QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類型:連續(xù)時(shí)間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR)
LTC6601IUF-1#TRPBF 功能描述:IC DRVR FILTER/ADC LN 20-QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類型:連續(xù)時(shí)間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR)
LTC6601IUF-1-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Confi gurable Filter/ADC Driver
LTC6601IUF-1-TRPBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Confi gurable Filter/ADC Driver
LTC6601IUF-2 制造商:LINER 制造商全稱:Linear Technology 功能描述:Low Power, Low Distortion, 5MHz to 27MHz, Pin Confi gurable Filter/ADC Driver
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