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參數(shù)資料
| 型號(hào)： | LTC6904MPMS8#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 68MHZ 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 1kHz ~ 68MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 7mA |
| 工作溫度： | -55°C ~ 125°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 安裝類型： | 表面貼裝 |
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LTC6903/LTC6904
10
69034fe
applicaTions inForMaTion
Output Control
The CLK and CLK outputs of the LTC6903/LTC6904 are
individually controllable through the serial port as de-
scribed in Table 2 below. The low power mode may also
be accessed through these control bits. It is preferred
that unused outputs be disabled in order to reduce power
dissipation and improve accuracy.
Disabling an unused output will improve accuracy of
operation at frequencies above 1MHz. An unused output
running with no load typically degrades frequency ac-
curacy up to 0.2% at 68MHz. An unused output running
into a 5pF load typically degrades frequency accuracy up
to 0.5% at 68MHz.
Table 2. Output Configuration
CNF1
CNF0
CLK
0
ON
CLK + 180°
0
1
OFF
ON
1
0
ON
OFF
1
Powered-Down*
*Powered-Down: When in this mode, the chip is in a low power state
and will require approximately 100s to recover. This is not the same
effect as the OE pin, which is fast, but uses more power supply current.
Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15
D14
D13
D12
D11
D10
D9
D8
OCT3
OCT2
OCT1
OCT0
DAC9
DAC8
DAC7
DAC6
D7
D6
D5
D4
D3
D2
D1
D0
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
CNF1
CNF0
Serial Port Register Description
OCT[3:0] – Frequency Divider Setting. (See Frequency
Setting Information Section)
DAC[9:0] – Master Oscillator Frequency Setting. (See
Frequency Setting Information Section)
CNF[1:0] – Output Configuration. This controls outputs
CLK and CLK according to Table 2.
LTC6903 SPI Compatible Interface
A serial data transfer is composed of sixteen (16) bits of
data labeled D15 through D0. D15 is the first bit of data
presented in each transaction. All serial port register bits
are set LOW on power-up.
Writing Data (LTC6903 Only)
When the SEN line is brought LOW, serial data presented
on the SDI input is clocked in on the rising edges of SCK
until SEN is brought HIGH. On every eighth rising edge
of SCK, the preceding 8-bits of data are clocked into the
internal register. It is therefore possible to clock in only
the 8 {D15 - D8} most significant bits of data rather than
completing an entire transfer.
The serial data transfer starts with the most significant
bit and ends with the least significant bit of the data, as
shown in the Timing Diagrams section.
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