參數(shù)資料
型號(hào): LTC6905HS5
廠商: LINEAR TECHNOLOGY CORP
元件分類: XO, clock
英文描述: 17MHz to 170MHz Resistor Set SOT-23 Oscillator
中文描述: PLL FREQUENCY SYNTHESIZER, PDSO5
封裝: PLASTIC, SOT-23, 5 PIN
文件頁數(shù): 5/8頁
文件大?。?/td> 119K
代理商: LTC6905HS5
LTC6905
5
6905fa
BLOCK DIAGRA
THEORY OF OPERATIOU
As shown in the Block Diagram, the LTC6905’s master
oscillator is controlled by the ratio of the voltage between
the V
+
and SET pins and the current entering the SET pin
(I
RES
). The voltage on the SET pin is forced to approxi-
mately 1V below V
+
by the PMOS transistor and its gate
bias voltage.
A resistor R
SET
, connected between the V
+
and SET pins,
“l(fā)ocks together” the voltage (V
+
– V
SET
) and current, I
RES
,
variation. This provides the LTC6905’s high precision. The
master oscillation frequency reduces to:
f
MHz
R
SET
k
MHz
MO
=
+
168 5
10
1 5
.
.
To extend the output frequency range, the master oscilla-
tor signal is divided by 1, 2 or 4 before driving OUT (Pin
5). The LTC6905 is optimized for use with resistors
between 10k and 25k, corresponding to oscillator fre-
quencies between 17.225MHz and 170MHz. The divide-
by value is determined by the state of the DIV input
(Pin 4). Tie DIV to V
+
or drive it to within 0.4V of V
+
to
select
÷
1. This is the highest frequency range, with the
Figure 1. R
SET
vs Output Frequency
master output frequency passed directly to OUT. The DIV
pin may be floated or driven to midsupply to select
÷
2, the
intermediate frequency range. The lowest frequency range,
÷
4, is selected by tying DIV to GND or driving it below
0.5V. Figure 1 shows the relationship between R
SET
,
divider setting and output frequency, including the over-
lapping frequencies.
OUTPUT FREQUENCY (MHz)
10
R
S
)
15
20
÷
4
÷
2
÷
1
6905 F01
10
5
60
110
160
30
25
+
+
+
1
3
GAIN = 1
V
+
V
BIAS
I
RES
I
RES
R
SET
SET
GND
MASTER OSCILLATOR
PROGRAMMABLE
DIVIDER
(
÷
1, 2 OR 4)
V
RES
= 1V
±
5%
+
– V
SET
)
THREE-STATE
INPUT DETECT
GND
V
+
15
μ
A
6905 BD
15
μ
A
OUT
DIVIDER
SELECT
5
DIV
4
2
f
OSC
= f
MO
N
相關(guān)PDF資料
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