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參數(shù)資料
| 型號(hào)： | LTC6907IS6#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 4MHZ TSOT23-6 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 40kHz ~ 4MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 305µA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-6 |
| 安裝類型： | 表面貼裝 |
10
LTC6907
6907fa
APPLICATIO S I FOR ATIO
WU
UU
Alternative Methods for Setting the Output Frequency
Any means of sinking current from the SET pin will control
the output frequency of the LTC6907. Equation 2 (re-
peated below) gives the fundamental relationship between
frequency and the SET pin voltage and current:
t
V
I
pF
OSC
SET
==
1
5
(2)
This equation shows that the LTC6907 converts conduc-
tance (ISET/VSET) to frequency or, equivalently, converts
resistance (RSET = VSET/ISET) to period.
VSET is the voltage across an internal diode, and as such
it is given approximately by:
V
Log
I
mV Log
I
A
mV C
SET
T
e
SET
S
e
SET
°
.
–.
/
–
25 9
82 10
23
18
where
VT = kT/q = 25.9mV at T = 300°K (27°C)
IS 82 10–18 Amps
(IS is also temperature dependent)
VSET varies with temperature and the SET pin current. The
response of VSET to temperature is shown in the Typical
Performance graphs. VSETchangesapproximately–2.3mV/
°C. At room temperature VSET increases 18mV/octave or
60mV/decade of increase in ISET.
If the SET pin is driven with a current source generating
ISET, the oscillator output frequency will be:
OSC
SET
e
SET
I
pF
mV
I
A
Log
5
25 9
82 10
18
.
–
2
23
./
mV C
°
Figure 12 and Figure 13 show a current controlled oscilla-
tor and a voltage controlled oscillator. These circuits are
not highly accurate if used alone, but can be very useful if
they are enclosed in an overall feedback circuit such as a
phase-locked loop.
0
A
TO 11.25
A
49.9k
V+
6907 F12
4MHz TO 400kHz
10k
V+
GND
DIV
OUT
GRD
SET
LTC6907
Figure 12. Current Controlled Oscillator
V+
GND
DIV
OUT
GRD
SET
LTC6907
RSET
56.2k
499k
VCTRL
0V TO 0.675V (VSET)
V+
4MHz TO 400kHz
6907 F13
Figure 13. Voltage Controlled Oscillator
Jitter and Divide Ratio
At a given output frequency, a higher master oscillator
frequency and a higher divide ratio will result in lower jitter
and higher power supply dissipation. Indeterminate jitter
percentage will decrease by a factor of slightly less than
the square root of the divider ratio, while determinate jitter
will not be similarly attenuated. Please consult the speci-
fication tables for typical jitter at various divider ratios.
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