VCC 5V 1 F 500 6910 F05b AGND LTC691" />
參數(shù)資料
型號(hào): LTC6910-1ITS8#TRPBF
廠商: Linear Technology
文件頁數(shù): 10/24頁
文件大小: 0K
描述: IC PGA DIGITAL R-R I/O TSOT23-8
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 可編程增益
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 16 V/µs
增益帶寬積: 11MHz
電壓 - 輸入偏移: 1500µV
電流 - 電源: 3.5mA
電流 - 輸出 / 通道: 35mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 10.5 V,±2.7 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8 薄型,TSOT-23-8
供應(yīng)商設(shè)備封裝: TSOT-23-8
包裝: 帶卷 (TR)
LTC6910-1
LTC6910-2/LTC6910-3
18
6910123fa
VCC 5V
1
F
500
6910 F05b
AGND
LTC6910-X
2
4
8
17.4k
Offset Nulling and Drift
Because internal op amp offset voltage VOS(OA) is gain
independent as noted above, offset trimming can be
readily added at the AGND pin, which drives the noninverting
input of the internal op amp. Such a trim shifts the AGND
voltage slightly from the system’s analog ground refer-
ence, where AGND would otherwise connect directly. This
is convenient when a low resistance analog ground poten-
tial or analog ground reference exists, for the return of a
voltage divider as in Figure 5a. When adjusted for zero DC
output voltage when the LTC6910-X has zero DC input
voltage, this DC nulling will hold at other gain settings also.
Figure 5a shows the basic arrangement for dual-supply
applications. A voltage divider (R1 and R2) scales external
reference voltages +VREF and –VREF to a range equaling or
slightly exceeding the approximately
±10mV op amp off-
set-voltage range. Resistor R1 is chosen to drop the
±10mV maximum trim voltage when the potentiometer is
set to either end. Thus if VREF is 5V, R1 should be about
100
. Note also that the two internal 10k resistors in
Figure 4 tend to bias AGND toward the mid-point of V+ and
V. The external voltage divider will swamp this effect if R1
is much less than 5k
. When considering the effect of the
internal 10k resistors, note that they form a Thévenin
equivalent of 5k in series with an open-circuit voltage at
the halfway potential (V+ + V)/ 2. (Although tightly matched,
these internal 10k resistors also have an absolute toler-
ance of up to
±30% and a temperature coefficient of
typically –30ppm/
°C.) Also, as described under Pin Func-
tions for AGND, a bypass capacitor C1 is always advisable
when AGND is not connected directly to a ground plane.
With this trim technique in place, the remaining DC offset
sources are drifts with temperature (typically 6
V/°C
referred to VOS(OA)), shifts in the LTC6910-X’s supply
voltage divided by the PSRR factors, supply voltage shifts
coupling through the two 10k internal resistors of
Figure 4, and of course any shifts in the reference voltages
that supply +VREF and –VREF in Figure 5a.
Figure 5b illustrates how to make an offset voltage adjust-
ment relative to the mid-supply potential in single supply
applications. Resistor values shown provide at least a
±10mV adjustment range assuming the minimum values
for the internal resistors at pin 2 and a supply potential of
5V. For single supply systems where all circuitry is DC
referenced to some other fixed bias potential, an offset
adjustment scheme is shown in Figure 5c. A low value for
R1 overrides the internal resistors at pin 2 and applies the
system DC bias to the LTC6910. Actual values for the
adjustment components depend on the magnitude of the
DC bias voltage. Offset adjustment component values
shown are an example with a single 5V VCC supply and a
1.25V system DC reference voltage.
Figure 5a. Offset Nulling
(Dual Supplies)
APPLICATIO S I FOR ATIO
WU
UU
R2
49.9k
C1
≥1F
ANALOG GROUND
REFERENCE
20k
R1
6910 F05a
AGND
–VREF
+VREF
LTC6910-X
2
Figure 5b. Offset Nulling
(Single Supply, Half Supply Reference)
Figure 5c. Offset Nulling
(Single Supply, External Reference)
VCC 5V
1.25V
SYSTEM DC REFERENCE
VOLTAGE
1
F
500
6910 F05c
AGND
LTC6910-X
2
4
8
976
4.64k
R1
100
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