V, V+
參數(shù)資料
型號: LTC6910-2ITS8#TRPBF
廠商: Linear Technology
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC PGA DIGITAL R-R I/O TSOT23-8
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 可編程增益
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 16 V/µs
增益帶寬積: 13MHz
電壓 - 輸入偏移: 1500µV
電流 - 電源: 3.5mA
電流 - 輸出 / 通道: 35mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 10.5 V,±2.7 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8 薄型,TSOT-23-8
供應(yīng)商設(shè)備封裝: TSOT-23-8
包裝: 帶卷 (TR)
LTC6910-1
LTC6910-2/LTC6910-3
16
6910123fa
V, V+ (Pins 4, 8): Power Supply Pins. The V+ and Vpins
should be bypassed with 0.1
F capacitors to an adequate
analog ground plane using the shortest possible wiring.
Electrically clean supplies and a low impedance ground
are important for the high dynamic range available from
the LTC6910-X (see further details under AGND). Low
noise linear power supplies are recommended. Switching
power supplies require special care to prevent switching
noise coupling into the signal path, reducing dynamic
range.
G0, G1, G2 (Pins 5, 6, 7): CMOS-Level Digital Gain-
Control Inputs. G2 is the most significant bit (MSB). These
pins control the voltage gain from IN to OUT pins (see
UU
U
PI FU CTIO S
Table 1, Table 2 and Table 3). Digital input code 000 causes
a “zero” gain with very low output noise. In this “zero” gain
state the IN pin is disconnected internally, but the OUT pin
remains active and forced by the internal op amp to the
voltage present on the AGND pin. Note that the voltage
gain from IN to OUT is inverting: OUT and IN pins always
swing on opposite sides of the AGND potential. The G pins
are high impedance CMOS logic inputs and must be
connected (they will float to unpredictable voltages if open
circuited). No speed limitation is associated with the
digital logic because it is memoryless and much faster
than the analog signal path.
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