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參數(shù)資料
| 型號： | LTC6915CDE#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PGA DIGITAL PREC 0DRFT 12DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.2 V/µs |
| 增益帶寬積： | 200kHz |
| 電流 - 輸入偏壓： | 4nA |
| 電壓 - 輸入偏移： | 5µV |
| 電流 - 電源： | 1.73mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 11 V，±1.35 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-DFN-EP（4x3） |
| 包裝： | 帶卷 (TR) |
LTC6915
12
6915fb
operaTion
TiMing DiagraM
D3
D2
D1
D0
D7 D4
D3
D4
D2
D1
D0
D7 D4
t6
t9
t7
t3
t5
t4
t1
t8
t2
PREVIOUS BYTE
CURRENT BYTE
CLK
DIN
CS/LD
DOUT
6915 TD
Theory of Operation (Refer to Block Diagrams)
The LTC6915 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (the sampling rate is 3kHz and the input switch-
on resistance is 1k to 2k, depending on the power supply
voltage). This capacitor’s charge is transferred to a sec-
ond internal hold capacitor (CH) translating the common
mode voltage of the input differential signal to that of
REF pin. The resulting signal is amplified by a zero-drift
op amp in the noninverting configuration. Gain control
within the amplifier occurs by switching resistors from a
matched resistor array. The LTC6915 has 14 levels of gain,
controlled by the parallel or serial interface. A feedback
capacitor CF helps to reduce the switching noise. Due to
the input sampling, an LTC6915 may produce aliasing
errors for input signals greater than 1.5kHz (one half the
3kHz sampling frequency). However, if the input signal is
bandlimited to less than 1.5kHz then an LTC6915 is useful
as instrumentation or as a differential to single-ended AC
amplifier with programmable gain.
Parallel Interface
As shown in Figure 1, connecting PARALLEL_SERIAL
to V+ allows the gain control code to be set through the
parallel lines (D3, D2, D1, D0). When HOLD_THRU is
low (referenced to DGND) or floating, the parallel gain
control bits (D3 ~ D0) directly control the PGA gain. When
HOLD_THRU is high, the parallel gain control bits are read
into and held by a 4-bit latch. Any change at D3 ~ D0 will
not affect the PGA gain when HOLD_THRU is high. Note
that the DFN12 package does not have the HOLD_THRU
pin. Instead, it is tied to DGND internally. The DOUT(D3)
pin is bidirectional (output in serial mode, input in parallel
mode). In parallel mode, the voltage at DOUT(D3) cannot
exceed V+; otherwise, large currents can be injected to V+
through the parasitic diode (see Figure 2). Connecting a
10kresistorattheDOUT(D3)pinifparallelmodeisselected
(see Figure 1) is recommended for current limiting.
Serial Interface
Connecting PARALLEL_SERIAL to V– allows the gain
control code to be set through the serial interface. When
CS is low, the serial data on DIN is shifted into an 8-bit
shift-register on the rising edge of the clock, with the MSB
transferred first (see Figure 3). Serial data on DOUT is
shifted out on the clock’s falling edge. A high CS will load
the 4 LSBs of the shift-register into a 4-bit D-latch, which
are the gain control bits. The clock is disabled internally
when CS is pulled high. Note: CLK must be low before CS
is pulled low to avoid an extra internal clock pulse.
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