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| 型號： | LTC6945IUFD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6945
12
6945f
OPERATION
Figure 5. Simplified Charge Pump Schematic
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter.
See Figure 5 for a simplified schematic of the charge pump.
inverting op amps in conjunction with positive-slope tuning
oscillators. A passive loop filter as shown in Figure 15,
used in conjunction with a positive-slope VCO, requires
CPINV = 0.
CHARGE PUMP FUNCTIONS
The charge pump contains additional features to aid
in system start-up and monitoring. See Table 6 for a
summary.
Table 6. CP Function Bit Descriptions
BIT
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPMID
Enable Mid-Voltage Bias
CPRST
Reset PFD
CPUP
Force Source Current
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0A enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge pump
sourcing current is disabled. Alternately, when CPCLO is
enabled and the CP pin voltage is less than approximately
0.9V, the TLO status flag is set, and the charge pump sinking
current is disabled. See Figure 5 for a simplified schematic.
The CPMID bit also found in register h0A enables a
resistive VCP+/2 output bias which may be used to pre-
bias troublesome loop filters into a valid voltage range
before attempting to lock the loop. When using CPMID,
it is recommended to also assert the CPRST bit, forcing
a PFD reset. Both CPMID and CPRST must be set to “0”
for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to “0”
to allow the loop to lock.
25
+
–
+
–
CP
THI
0.9V
VCP
+
VCP
+
TLO
+
–
0.9V
6945 F05
+
–
VCP
+/2
CPMID
CPUP
UP
CPDN
DOWN
The output current magnitude ICPmaybesetfrom250μAto
11.2mA using the CP[3:0] bits found in serial port register
h09. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Table 5 for programming specifics and the Applications
Information section for loop filter examples.
Table 5. CP[3:0] Programming
CP[3:0]
ICP
0
250μA
1
350μA
2
500μA
3
700μA
4
1.0mA
5
1.4mA
6
2.0mA
7
2.8mA
8
4.0mA
9
5.6mA
10
8.0mA
11
11.2mA
12 to 15
Invalid
The CPINV bit found in register h0A should be set for ap-
plications requiring signal inversion from the PFD, such
as for loops using negative-slope tuning oscillators, or
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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