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參數(shù)資料
| 型號： | LTC694CN8-3.3#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | LTC694CN8-3.3#TRPBF |
LTC694-3.3/LTC695-3.3
11
69453fb
APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond VCC due
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC.
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
STATUS
VCC
C2 monitors VCC for active switchover.
VOUT
VOUT is connected to VBATT through an internal PMOS switch.
VBATT
The supply current is 1μA maximum.
BATT ON
Logic high. The open-circuit output voltage is equal to VOUT.
PFI
Power failure input is ignored.
PFO
Logic low.
RESET
Logic low.
RESET
Logic high. The open-circuit output voltage is equal to VOUT.
LOW
_
LINE Logic low.
WDI
Watchdog input is ignored.
WDO
Logic high. The open-circuit output voltage is equal to VOUT.
CE IN
Chip
_
Enable input is ignored.
CE OUT
Logic high. The open-circuit output voltage is equal to VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by pre-
venting write operations when VCC is at invalid level. Two
additional pins, CE IN and CE OUT, control the Chip
_
Enable
or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT
follows CE IN with a typical propagation delay of 30ns.
When VCC falls below the reset voltage threshold or VBATT,
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the VBATT Pin to Ground
While the Battery is Removed, Eliminating Spurious Resets
2.7M
0.1μF
VBATT
LTC694-3.3
LTC695-3.3
GND
694/5-3.3 F04
10Ω
VCC
V1
CE IN
VOUT = VBATT
CE OUT
VOUT = VBATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
694/5-3.3 F05
Figure 5. Timing Diagram for CE IN and CE OUT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC694CN8PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC694CN8-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC694CS-3.3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Power Supply Supervisor |
| LTC694CS8 | 功能描述:IC MPU SUPERVISORY CIRCUIT 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:高有效 復(fù)位超時(shí):- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| LTC694CS8#PBF | 功能描述:IC MPU SUPERVISORY CIRCUIT 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 其它有關(guān)文件:STM6905 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 類型:多壓監(jiān)控器 監(jiān)視電壓數(shù)目:5 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時(shí):最小為 140 ms 電壓 - 閥值:2.188V，2.955V，可調(diào)，可調(diào)，可調(diào) 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1197 (CN2011-ZH PDF) 其它名稱:497-8728-6 |
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