V
參數(shù)資料
型號(hào)： LTC6991IS6#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 0K
描述： IC OSC SILICON 977HZ TSOT23-6
產(chǎn)品培訓(xùn)模塊： TimerBlox Family Timing Devices
產(chǎn)品目錄繪圖： LTC699_TSOT-23
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 2,500
系列： TimerBlox®
類型： 振蕩器 - 硅
頻率： 29.1µHz ~ 977Hz
電源電壓： 2.25 V ~ 5.5 V
電流 - 電源： 135µA
工作溫度： -40°C ~ 85°C
封裝/外殼： SOT-23-6 細(xì)型，TSOT-23-6
包裝： 帶卷 (TR)
供應(yīng)商設(shè)備封裝： TSOT-23-6
安裝類型： 表面貼裝
配用： DC1562A-B-ND - BOARD EVAL LTC6991
LTC6991
7
6991fb
Output Resistance
vs Supply Current
Typical Start-Up with POL = 1
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
SUPPLY VOLTAGE (V)
OUTPUT
RESIST
ANCE
(Ω)
6991 G22
50
25
20
35
45
5
10
15
30
40
0
24
35
6
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
V+
1V/DIV
OUT
1V/DIV
250μs/DIV
V+ = 2.5V
DIVCODE = 15
RSET = 50k
6991 G19
500μs
1μs (tMASTER) WIDE
INITIAL PULSE
PIN FUNCTIONS (DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This
supply should be kept free from noise and ripple. It should
be bypassed directly to the GND pin with a 0.1μF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. A V+ referenced A/D converter monitors the DIV
pin voltage (VDIV) to determine a 4-bit result (DIVCODE).
VDIV may be generated by a resistor divider between V+
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
VDIV settles quickly. The MSB of DIVCODE (POL) deter-
mines the polarity of the RST and OUT pins. If POL = 0,
RST is active-high, and forces OUT low. If POL = 1, RST
is active-low and forces OUT high.
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) pro-
grams the master oscillator frequency. The ISET current
range is 1.25μA to 20μA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor con-
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
6991 PF
LTC6991
RST
GND
SET
OUT
V+
DIV
C1
0.1μF
RSET
R2
R1
V+
RST (Pin 4/Pin 1): Output Reset. The behavior of the RST
pin is dependent on the polarity bit (POL). The POL bit is
configured via the DIVCODE setting. When POL = 0, set-
ting RST high forces OUT low and setting RST low allows
the output to oscillate. When POL = 1, RST is active low.
In that case, setting RST low forces OUT high and setting
RST high allows the output to oscillate.
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