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參數(shù)資料
型號： LTC6992CDCB-3#TRPBF
廠商： Linear Technology
文件頁數(shù)： 14/34頁
文件大小： 0K
描述： IC OSC SILICON 1MHZ 6-DFN
產(chǎn)品培訓(xùn)模塊： TimerBlox Family Timing Devices
產(chǎn)品目錄繪圖： LTC699_DFN
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 2,500
系列： TimerBlox®
類型： 振蕩器 - 硅
頻率： 3.81Hz ~ 1MHz
電源電壓： 2.25 V ~ 5.5 V
電流 - 電源： 365µA
工作溫度： 0°C ~ 70°C
封裝/外殼： 6-WFDFN 裸露焊盤
包裝： 帶卷 (TR)
供應(yīng)商設(shè)備封裝： 6-DFN-EP（2x3）
安裝類型： 表面貼裝
配用： DC1562A-C-ND - BOARD EVAL LTC6992-1
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
21
69921234fc
applicaTions inForMaTion
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25μA to 20μA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET<1.25A.Atapproximately500nA,theoscillatoroutput
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
while frequency modulating a very low frequency output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Pulse Width Modulation Bandwidth and Settling Time
TheLTC6992hasawidePWMbandwith,makingitsuitable
for a variety of feedback applications. Figure 10 shows that
the frequency response is flat for modulation frequencies
up to nearly 1/10 of the output frequency. Beyond that
point, some peaking may occur (depending on NDIV and
average duty cycle setting).
Duty cycle settling time depends on the master oscillator
frequency. Following a ±80mV step change in VMOD, the
duty cycle takes approximately eight master clock cycles
(8 tMASTER) to settle to within 1% of the final value.
Examples are shown in Figures 11a and 11b.
Figure 10. PWM Frequency Response
Figure 11a. PWM Settling Time, 25% Duty Cycle
Figure 11b. PWM Settling Time, 50% Duty Cycle
fMOD/fOUT (Hz/Hz)
0.001
D(f
MOD
)/D(0Hz)
(dB)
10
5
–5
0
–10
–15
–20
0.01
6992 F10
1
0.1
÷1, 50%
÷1, 80%
÷16
÷4, 50%
÷4, 15%
VMOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
V+ = 3.3V
DIVCODE = 0
RSET = 200k
VMOD = 0.3V ±40mV
10s/DIV
6992 F11a
VMOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
V+ = 3.3V
DIVCODE = 0
RSET = 200k
VMOD = 0.5V ±40mV
10s/DIV
6992 F11b
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