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參數(shù)資料
型號(hào): LTC6994CS6-2#TRMPBF
廠商: Linear Technology
文件頁(yè)數(shù): 8/26頁(yè)
文件大?。?/td> 0K
描述: IC DELAY LINE TSOT-23-6
產(chǎn)品培訓(xùn)模塊: TimerBlox Family Timing Devices
產(chǎn)品目錄繪圖: LTC699_TSOT-23
特色產(chǎn)品: TimerBlox?
標(biāo)準(zhǔn)包裝: 1
系列: TimerBlox®
功能: 可編程
可用的總延遲: 1µs ~ 33.6s
獨(dú)立延遲數(shù): 1
電源電壓: 2.25 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6 細(xì)型,TSOT-23-6
供應(yīng)商設(shè)備封裝: TSOT-23-6
包裝: 標(biāo)準(zhǔn)包裝
配用: DC1562A-E-ND - BOARD EVAL LTC6992-3
其它名稱: LTC6994CS6-2#TRMPBFDKR
LTC6994-1/LTC6994-2
16
699412fb
applicaTions inForMaTion
Basic Operation
The simplest and most accurate method to program the
LTC6994 is to use a single resistor, RSET, between the SET
and GND pins. The design procedure is a 3-step process.
Alternatively, Linear Technology offers the easy-to-use
TimerBlox Designer tool to quickly design any LTC6994
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
Choose LTC6994-1 to delay one (rising or falling) input
transition. The POL bit then defines which edge is to be
delayed. POL = 0 delays rising edges. POL = 1 delays
falling edges.
Choose LTC6994-2 to delay rising and falling edges. Set
POL = 0 for normal operation, or POL = 1 to invert the
output.
Step 2: Select the NDIV Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given delay time (tDELAY), NDIV should
be selected to be within the following range:
tDELAY
16s
≤NDIV
tDELAY
1s
(1)
To minimize supply current, choose the lowest NDIV value.
However,insomecasesahighervalueforNDIVwillprovide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate NDIV
values for the desired tDELAY.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET.
The final step is to calculate the correct value for RSET
using the following equation:
RSET =
50k
1s
tDELAY
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a circuit to delay falling edges by
tDELAY = 100s with minimum power consumption.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
To delay negative transitions, choose the LTC6994-1 with
POL = 1.
Step 2: Select the NDIV Frequency Divider Value.
Choose an NDIV value that meets the requirements of
Equation (1), using tDELAY = 100s:
6.25 ≤ NDIV ≤ 100
Potential settings for NDIV include 8 and 64. NDIV = 8 is
the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 1 and NDIV = 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and R2
= 976k values to program DIVCODE = 14.
Step 3: Select RSET.
Calculate the correct value for RSET using Equation (2).
RSET =
50k
1s
100s
8
= 625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in tDELAY is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 9.
Figure 9. 100s Negative-Edge Delay
LTC6994-1
IN
GND
SET
OUT
V+
DIV
R1
102k
0.1F
DIVCODE = 14
699412 F09
2.25V TO 5.5V
R2
976k
RSET
625k
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