3
LTC7541A
VDD = 15V, VREF = 10V, OUT 1 = OUT 2 = GND = 0V, TA = TMIN to TMAX, unless otherwise specified.
The q denotes specifications which apply over the full operating
temperature range.
Note 1:
±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design, not subject to test.
Note 4: IOUT1 with all digital inputs = 0V or IOUT2 with all digital
inputs = VDD.
Note 5: OUT 1 load = 100
in parallel with 13pF.
Note 6: Measured from digital input change to 90% of final analog value.
Digital inputs = 0V to VDD or VDD to 0V.
Note 7: VREF = 0V. All digital inputs 0V to VDD or VDD to 0V. Measured
using LT1363 as output amplifier.
ELECTRICAL CHARACTERISTICS
BLOCK DIAGRAM
W
40k
10k
40k
20k
40k
20k
40k
20k
40k
DECODER
BIT 1
(MSB)
BIT 2
GND
VDD
VREF
RFB
BIT 3
BIT 4
BIT 12
(LSB)
OUT 1
OUT 2
7541 BD
TTL/DTL/CMOS COMPATIBLE DIGITAL INPUTS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ALL GRADES
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
VDD
Operating Supply Range
q
515
16
V
IDD
Suppy Current
Digital Inputs = VIH or VIL
q
2mA
Digital Inputs = 0V or VDD
q
100
A
Digital Inputs
VIH
Digital Input High Voltage
q
2.4
V
VIL
Digital Input Low Voltage
q
0.8
V
IIN
Digital Input Current
q
0.001
±1
A
CIN
Digital Input Capacitance
(Note 3), VIN = 0V
q
8pF
AC Performance
Propagation Delay
(Notes 5, 6)
100
ns
Digital-to-Analog Glitch Impulse
(Notes 5, 7)
1000
nV-sec
Multiplying Feedthrough Error
VREF = ±10V, 10kHz Sinewave
1.0
mVP-P
Output Current Settling Time
(Note 5), To 0.01% for Full-Scale Change
0.6
s
COUT
Output Capacitance (Note 3)
Digital Inputs = VIH
COUT1
q
200
pF
COUT2
q
70
pF
Digital Inputs = VIL
COUT1
q
70
pF
COUT2
q
200
pF