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參數(shù)資料
| 型號： | LTPC |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 100mA REGULATED CHARGE-PUMP INVERTERS IN THINSOT |
| 中文描述： | 100mA的穩(wěn)壓電荷泵采用ThinSOT逆變器中 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 188K |
| 代理商： | LTPC |
LTC1983-3/LTC1983-5
8
sn1983 1983fs
Inrush Currents
During normal operation, V
IN
will experience current tran-
sients in the several hundred milliamp range whenever the
charge pump is enabled. During start-up, these inrush
currents may approach 1 to 2 amps. For this reason, it is
important to minimize the source resistance between the
input supply and the V
IN
pin. Too much source resistance
may result in regulation problems or even prevent start-
up. One way that this can be avoided (especially when the
source impedance can’t be lowered due to system con-
straints) is to use a large V
IN
capacitor with low ESR right
at the V
IN
pin. If ceramic capacitors are used, you may
need to add 1
μ
F to 10
μ
F tantalum capacitor in parallel to
limit input voltage transients. Input voltage transients will
occur if V
IN
is applied via a switch or a plug. One example
of this situation is in USB applications.
Ultralow Quiescent Current Regulated Supply
The LTC1983 contains an internal resistor divider (refer to
the Block Diagram) that draws only 1
μ
A (typ for the 3V
version) from V
OUT
during normal operation. During shut-
down, the resistor divider is disconnected from the output
and the part draws only leakage current from the output.
During no-load conditions, applying a 1Hz to 100Hz, 2%
to 5% duty cycle signal to the SHDN pin ensures that the
circuit of Figure 2 comes out of shutdown frequently
enough to maintain regulation even under low-load condi-
tions. Since the part spends nearly all of its time in
shutdown, the no-load quiescent current is essentially
zero. However, the part will still be in operation during the
time the SHDN pin is high, so the current will not be zero
and can be calculated using the following equations to
determine the approximate maximum current: I
IN(MAX)
=
[(Time out of shutdown) (Burst Mode operation quies-
cent current) + (Normal operating I
IN
) (Time output is
being charged before the LTC1983 enters Burst Mode
operation)]/(Period of SHDN signal). This number will be
highly dependent on the amount of board leakage current
and how many devices are connected to V
OUT
(each will
draw some leakage current) and must be calculated and
verified for each different board design.
The LTC1983 must be out of shutdown for a minimum
duration of 200
μ
s to allow enough time to sense the output
and keep it in regulation. A 1Hz, 2% duty cycle signal will
keep V
OUT
in regulation under no-load conditions. Even
though the term no-load is used, there will always be board
leakage current and leakage current drawn by anything
connected to V
OUT
. This is why it is necessary to wake the
part up every once in a while to verify regulation. As the
V
OUT
load current increases, the frequency with which the
part is taken out of shutdown must also be increased to
prevent V
OUT
from drooping below the –2.88V (for the 3V
version) during the OFF phase (see Figure 3). A 100Hz, 2%
duty cycle signal on the SHDN pin ensures proper regula-
tion with load currents as high as 100
μ
A. When load
current greater than 100
μ
A is needed, the SHDN pin must
be forced high as in normal operation.
Each time the LTC1983 comes out of shutdown, the part
delivers a minimum of one clock cycle worth of charge to
the output. Under high V
IN
(>4V) and/or low I
OUT
(<10
μ
A)
conditions, this behavior may cause a net excess of charge
to be delivered to the output capacitor if a high frequency
signal is used on the SHDN pin (e.g., 50Hz to 100Hz).
Under such conditions, V
OUT
will slowly drift positive and
may even go out of regulation. To avoid this potential
Figure 2. Ultralow Quiescent Current Regulated Supply
V
IN
GND
C
+
SHDN
V
OUT
C
–
LTC1983-3
C
FLY
1
F
CERAMIC
FROM MPU
SHDN
V
IN
C
IN
10
μ
F
TANTALUM
C
OUT
10
F
CERAMIC
SHDN PIN WAVEFORMS:
LOW I
Q
MODE
(I
OUT
≤
100
μ
A)
V
OUT
LOAD ENABLE MODE
(I
OUT
= 100
μ
A TO 100mA)
(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
–3V
±
4%
1983 F02
3.3V TO 5.5V
OPERATIOU
(Refer to Block Diagram)
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