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參數(shù)資料
| 型號(hào)： | LUCL9312AP-DT |
| 英文描述： | PLCC-Socket-Adapter 32-pin DIL to 32-pin PLCC for 8-Bit EPROMs |
| 中文描述： | 線路接口和線路接入電路轉(zhuǎn)發(fā)電池SLIC和振鈴繼電器的訓(xùn)練班- 57應(yīng)用 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 709K |
| 代理商： | LUCL9312AP-DT |
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Data Sheet
July 2001
Forward Battery SLIC and Ringing Relay for TR-57 Applications
L9312 Line Interface and Line Access Circuit
18
Agere Systems Inc.
Electrical Characteristics
(continued)
Logic Inputs and Outputs, V
DD
= 5.0 V
Table 9. Logic Inputs and Outputs
Timing Requirements
Table 10. Timing Requirements
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t
SU
ns before LATCH goes low and held t
HL
ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, and B2. The
data control inputs at B0, B1, and B2, may only be changed when LATCH is high. NSTAT supervision output is not
controlled by the LATCH control input.
12-3526(F)
Figure 3. Timing Requirements
Parameter
Symbol
V
IL
V
IH
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
Input Current:
Low Level (V
DD
= 5.25 V, V
I
= 0.4 V)
High Level (V
DD
= 5.25 V, V
I
= 2.4 V)
Output Voltages (CMOS):
Low Level (V
DD
= 4.75 V, I
OL
= 180
μ
A)
High Level (V
DD
= 4.75 V, I
OH
=
–
20
μ
A)
–
0.5
2.0
0.4
2.4
0.7
V
DD
V
V
I
IL
I
IH
—
—
—
—
±
50
±
50
μ
A
μ
A
V
OL
V
OH
0
2.4
0.2
—
0.4
V
CC
V
V
Parameter
Symbol
t
SU
t
HL
Min
200
50
Typ
—
—
Max
—
—
Unit
ns
ns
Minimum Setup Time from B0, B1, B2 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2
t
SU
t
HL
LATCH
B0, B1,
B2, B3
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