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參數(shù)資料
| 型號： | LUCW3000CCN-TR |
| 英文描述： | W3000 PLL Dual-Band Frequency Synthesizer |
| 中文描述： | W3000鎖相環(huán)雙頻段頻率合成器 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 327K |
| 代理商： | LUCW3000CCN-TR |
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Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
11
REF Register
This section describes each bit of the reference register. The REF register is used for programming the division
ratio of the reference clock and for initial setup of the operation modes.
Table 7. REF Register Bit Description (C0 = 1, C1 = 0)
Bit
1
2:12
13
14
15:16
17
18:19
20
21
22
23
24
Name
C0 = 1
R[1:11]
D1
D2
D3, D4
D5
D6, D7
RE
ERES
EN1
LD
C1 = 0
Description
Register address bit. C0 = 1 for REF (last bit in serial sequence).
Reference frequency divide ratio.
Forced counter reload programming (synchronous/asynchronous).
Charge pump disable function.
Programable charge pump current for frequency band 2.
Phase detector polarity.
Programable charge pump current for frequency band 1.
Reset for first programming after powerup (1 = reset).
Enables external resistor (on RES pin) to set charge pump current.
Enable W3000. (0 is powerdown.)
Lock detect output enable.
Secondary address bit (first bit in serial sequence).
Table 8. REF Register
Last bit in serial sequence
1
2
R
1
3
R
2
4
R
3
5
R
4
6
R
5
7
R
6
8
R
7
9
R
8
10
R
9
11
R
10
12
R
11
13
D
1
14
D
2
15
D
3
16
D
4
17
D
5
18
D
6
19
D
7
20
RE ERES EN LD
21
22
23
24
C1
= 0
C0
= 1
Table 9. R1:R11:
Reference Divider Ratio (Bits 2 to 12)
R11
—
0
0
.
.
.
1
R10
—
0
0
.
.
.
1
R9
—
0
0
.
.
.
1
R8
—
0
0
.
.
.
1
R7
—
0
0
.
.
.
1
R6
—
0
0
.
.
.
1
R5
—
0
0
.
.
.
1
R4
—
0
0
.
.
.
1
R3
—
0
0
.
.
.
1
R2
—
1
1
.
.
.
1
R1
—
0
1
.
.
.
1
Divide Ratio R
—*
2
3
.
.
.
2047
*The reference counter cannot operate with division numbers less than 2.
First bit in serial sequence
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