參數(shù)資料
型號(hào)： LUPXA255A0C300
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, PBGA256
封裝： 17 X 17 MM, 1.75 MM HEIGHT, LEAD FREE, PLASTIC, BGA-256
文件頁(yè)數(shù)： 9/46頁(yè)
文件大?。?/td> 1302K
代理商： LUPXA255A0C300
Package Information
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
17
nRESET_OUT
OC
Reset out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is de-asserted but before
the first instruction fetch. nRESET_OUT is also asserted
for “soft” reset events: sleep, watchdog reset, or GPIO
reset.
Driven low during
any reset sequence
- driven high prior to
first fetch.
Driven Low
JTAG and Test Pins
nTRST
IC
JTAG test interface reset. Resets the JTAG/debug port.
If JTAG/debug is used, drive nTRST from low to high
either before or at the same time as nRESET. If JTAG is
not used, nTRST must be either tied to nRESET or tied
low.
Input
TDI
IC
JTAG test data input. (input) Data from the JTAG
controller is sent to the PXA255 processor using this pin.
This pin has an internal pull-up resistor.
Input
TDO
OCZ
JTAG test data output. (output) Data from the PXA255
processor is returned to the JTAG controller using this
pin.
Hi-Z
TMS
IC
JTAG test mode select. (input) Selects the test mode
required from the JTAG controller. This pin has an
internal pull-up resistor.
Input
TCK
IC
JTAG test clock. (input) Clock for all transfers on the
JTAG test interface.
Input
TEST
IC
Test Mode. (input) Reserved. Must be grounded.
Input
TESTCLK
IC
Test Clock. (input) Reserved. Must be grounded.
Input
Power and Ground Pins
VCC
SUP
Positive supply for internal logic. Must be connected
to the low voltage supply on the PCB.
Powered
Note [6]
VSS
SUP
Ground supply for internal logic. Must be connected to
the common ground plane on the PCB.
Grounded
PLL_VCC
SUP
Positive supply for PLLs and oscillators. Must be
connected to the common low voltage supply.
Powered
Note [6]
PLL_VSS
SUP
Ground supply for the PLL. Must be connected to
common ground plane on the PCB.
Grounded
VCCQ
SUP
Positive supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
3.3v supply on the PCB.
Powered
Note [7]
VSSQ
SUP
Ground supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Grounded
VCCN
SUP
Positive supply for memory bus and PCMCIA pins.
Must be connected to the common 3.3v or 2.5v supply on
the PCB.
Powered
Note [7]
VSSN
SUP
Ground supply for memory bus and PCMCIA pins.
Must be connected to the common ground plane on the
PCB.
Grounded
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
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