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參數(shù)資料
| 型號(hào)： | LV49821VH-TLM-H |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 0K |
| 描述： | IC AMP AUDIO CLASS D BTL 13HSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | AB 類 |
| 輸出類型： | 2-通道（立體聲）帶立體聲耳機(jī) |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 1.4W x 2 @ 8 歐姆 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 特點(diǎn)： | 待機(jī)，熱保護(hù) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 13-HSSOP |
| 封裝/外殼： | 16-LSSOP（0.173"，4.40mm 寬）13 引線 |
| 包裝： | 帶卷 (TR) |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6146 Rev. 1.1.0
9
FMS6146
—
Low-Cost
Six-Channel
4th-Order
Standard
De
nition
V
ideo
Filter
Driver
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6146DEMO,
to guide layout and aid device testing and characterizati-
on. The FMS6146DEMO is a four-layer board with full
power and ground planes. Following this layout congu-
ration provides the optimum performance and thermal
characteristics. For optimum results, follow the guidelines
below as a basis for high-frequency layout:
Include 1μF and 0.1μF ceramic bypass capacitors.
Place the 1μF capacitor within 0.75 inches of the
power pin.
Place the 0.1μF capacitor within 0.1 inches of the
power pin.
For multi-layer boards, use a large ground plane to help
dissipate heat.
For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches.
Minimize all trace lengths to reduce series inductances.
■
Output Considerations
The FMS6146 outputs are DC offset from the input by
150mV. Therefore, V
OUT = 2VIN DC+150mV. This offset is
required to obtain optimal performance from the output dri-
ver and is held at the minimum value to decrease the stan-
ding DC current into the load. Since the FMS6146 has a 2x
(6dB) gain, the output is typically connected via a 75Ω-
series back-matching resistor, followed by the 75Ω video
cable. Due to the inherent divide by two of this congurati-
on, the blanking level at the load of the video signal is
always less than 1V. When AC-coupling the output, ensure
that the coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time dis-
tortion (video tilt) is kept as low as possible.
The selection of the coupling capacitor is a function of the
subsequent circuit input impedance and the leakage cur-
rent of the input being driven. To obtain the highest quality
output video signal, the series termination resistor must be
placed as close to the output pin as possible. This reduces
the parasitic capacitance and inductance effect on the out-
put driver. The distance from the device pin to the series
termination resistor should be no greater than 0.1 inches.
Figure 16. Distance from Device Pin to Series
Termination Resistor
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