LV8112V
No.A1645-11/13
3-phase Logic Truth Table
(IN = “H” indicates the state where in IN+ > IN)
F/R = H
F/R = L
Output
IN1
IN2
IN3
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
L
H
M
H
L
H
L
M
H
L
H
M
L
H
L
H
L
H
L
H
L
M
L
H
L
H
M
L
H
L
M
H
L
S/S Pin
BRSEL Pin
Input state
Mode
Input state
While stopped
High or Open
Stop
High or Open
Free run
Low
Start
Low
Short-circuit brake
CSDSEL Pin
SDCC Select
Input state
Mode
Input state
Mode
High or Open
LD standard
F/R = High or Open
Function ON
Low
FG standard
F/R = Low
Function OFF
LV8112V Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls
by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
fFG (Servo) = fCLK
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. The output transistor is always
saturated while the transistor is on and adjusts the driving force of the motor by changing the duty that the output
transistor is on.
The PWM switching of the output is performed by the upper-side output transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister)).
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since
the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this
delay.
It is necessary to set the current increases by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs.
If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of
motor if the motor constrained protection circuit does operate. (Clock disconnection protection)