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參數(shù)資料
| 型號(hào)： | LV8573AM |
| 廠(chǎng)商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | LV8573AM |
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Functional Description
(Continued)
D0–D1:
These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
LY1
LY0
Leap Year
Counter
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
D2:
The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
D3:
This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter’s prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped. When the
RTC is initially powered up this bit will be held at a logic 0
until the oscillator starts functioning correctly after which
this bit may be modified. If an oscillator fail event occurs,
this bit will be reset to logic 0.
D4:
This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Note
that the MFO pin is configured as open drain in standby
mode.
If bit D4 is set to a zero then the interrupt control register
and the periodic interrupt flag will be reset when the RTC
enters the standby mode (V
BB
l
V
CC
). They will have to be
re-configured when system (V
CC
) power is restored.
D5–D7:
General purpose RAM bits.
OUTPUT MODE REGISTER
TL/F/11418–16
D0–D6:
General purpose RAM bits.
D7:
This bit is used to program the signal appearing at the
MFO output, as follows:
D7
MFO Output Signal
0
1
Power Fail Interrupt
Buffered Crystal Oscillator
INTERRUPT CONTROL REGISTER 0
TL/F/11418–17
D0–D5:
These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subse-
quent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
D6 and D7:
General purpose RAM.
INTERRUPT CONTROL REGISTER 1
TL/F/11418–18
D0–D5:
Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the ‘‘a(chǎn)lways equal’’ state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Regis-
ter, all bits must be written to a logic zero.
D6:
In order to generate an external alarm compare inter-
rupt to the
m
P from bit D3 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected, then this bit is controlled by D4 of the Real Time
Mode Register.
D7:
The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the
m
P when a V
BB
l
V
CC
. If battery
backed mode is selected, then this bit is controlled by D4 of
the Real Time Mode Register.
12
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