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參數(shù)資料
| 型號(hào)： | LV8573AV |
| 廠(chǎng)商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大小： | 306K |
| 代理商： | LV8573AV |
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AC Electrical Characteristics
V
CC
e
3.3V
g
10%, V
BB
e
2.5V, V
PFAIL
l
V
IH
, C
L
e
100 pF unless otherwise specified
Symbol
Parameter
Min
Max
Units
READ TIMING
t
AR
Address Valid Prior to Read Strobe
10
ns
t
RW
Read Strobe Width (Note 8)
100
ns
t
CD
Chip Select to Data Valid Time
100
ns
t
RAH
Address Hold after Read (Note 9)
2
ns
t
RD
Read Strobe to Valid Data
90
ns
t
DZ
Read or Chip Select to TRI-STATE
80
ns
t
RCH
Chip Select Hold after Read Strobe (Note 9)
0
ns
t
DS
Minimum Inactive Time between Read or Write Accesses
70
ns
WRITE TIMING
t
AW
Address Valid before Write Strobe
10
ns
t
WAH
Address Hold after Write Strobe (Note 9)
2
ns
t
CW
Chip Select to End of Write Strobe
110
ns
t
WW
Write Strobe Width (Note 10)
100
ns
t
DW
Data Valid to End of Write Strobe
70
ns
t
WDH
Data Hold after Write Strobe (Note 9)
2
ns
t
WCH
Chip Select Hold after Write Strobe (Note 9)
0
ns
INTERRUPT TIMING
t
ROLL
Clock rollover to INTR out typically 20
m
s
Note 8:
Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9:
Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10:
Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
GND to 3.0V
6 ns (10%–90%)
1.3V
Active High
a
0.5V
Active Low
b
0.5V
Note 11:
C
L
e
100 pF, includes jig and scope capacitance.
Note 12:
S1
e
V
CC
for active low to high impedance measurements.
S1
e
GND for active high to high impedance measurements.
S1
e
open for all other timing measurements.
Capacitance
(T
A
e
25
§
C, f
e
1 MHz)
Symbol
Parameter
(Note 13)
Typ
Units
C
IN
Input Capacitance
5
pF
C
OUT
Output Capacitance
7
pF
Note 13:
This parameter is not 100% tested.
Note 14:
Output rise and fall times 25 ns max (10%–90%) with 100 pF load.
TL/F/11418–2
3
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