參數(shù)資料
型號(hào)： LX1725ILQ-TR
廠商： MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP
元件分類： 音頻／視頻放大
英文描述： 16 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC32
封裝： 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MLPQ-32
文件頁(yè)數(shù)： 17/23頁(yè)
文件大小： 377K
代理商： LX1725ILQ-TR
LX1725
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
3
Page
WWW
.Microse
m
i
.CO
M
15W+15W Stereo Class-D Amplifier
Filterless 30W Mono in BTL
Copyright
2004
Rev. 1.2, 2005-12-06
TM
FUNCTIONAL PIN DESCRI PTION (CONTINUED)
Name
Description
VNEGA
Analog voltage sense for VNEG voltage. Needs to be protected from noise at VNEG1 and VNEG2. Typically,
about 180A is sourced out of this pin.
IN2P
Positive audio input for channel 2. The input signal should be AC-coupled into this pin. The DC bias voltage will
be equal to VREF. The input impedance to VREF will be about 17Kohm.
IN2M
Negative audio input for channel 2. The input signal should be AC-coupled into this pin. The DC bias voltage will
be equal to VREF. The input impedance to VREF will be about 17Kohm.
OUTREF2
Negative feedback input pin for channel 2. Normally connected to VCOM.
VGND
Ground reference return for the analog +5V power supply. This supply is allowed to “float” between VNEG and
VCOM. Typical current out of this pin is about 600A.
MUTE
Tri-level control pin. When this pin is set to greater than V5V/2, the audio signal path is muted. For voltages
between V5V/4 and V5V/2, the audio gain will be set to approximately 5V/V. This allows the “Low Gain” mode to
be tested. For voltages less than V5V/4, the normal 10V/V gain is in place.
MASTER
Quad-level control pin. This pin has three thresholds to enable Master/Slave and the “Quick” test mode. Quick
mode forces the internal 65224 clock counter to be bypassed in order to speed-up production testing.
Here is how the various modes are mapped:
V @ Master
Mode
< V5V/4
Slave, Normal Mode
< V5V/2, >V5V/4
Slave, Quick mode
< 3*V5V/4, >V5V/2
Master, Quick mode
> 3*V5V/4
Master, Normal mode
Normally, this pin should be shorted to either V5V or GND.
VPOS2
Positive voltage supply to channel 2’s output buffer. In a split supply system, this voltage will range between +5V
up to +15V. In a single supply system, this voltage is allowed to be +10V up to +30V. Power supply de-coupling
capacitance should be placed between VPOS2 and VNEG2.
OUT2
PWM output for channel 2. This pin drives the L-C low pass filter prior to driving the speaker.
VNEG2
Negative voltage supply to channel 2’s output buffer. In a split supply system, this voltage will range between –
5V down to –15V. In a single supply system, this represents the 0V point.
VNEG1
Negative voltage supply to channel 1’s output buffer. In a split supply system, this voltage will range between –
5V down to –15V. In a single supply system, this represents the 0V point.
OUT1
PWM output for channel 1. This pin drives the L-C low pass filter prior to driving the speaker.
VPOS1
Positive voltage supply to channel 1’s output buffer. In a split supply system, this voltage will range between +5V
up to +15V. In a single supply system, this voltage is allowed to be +10V up to +30V. Power supply de-coupling
capacitance should be placed between VPOS1 and VNEG1.
STBY
A logic high as this pin forces a zero current standby mode. CMOS logic levels.
VCOM
Mid-voltage supply for both channel 1 and channel 2. This voltage should be half way between VPOS and
VNEG. De-coupling capacitance should be placed between this pin and both VPOS and VNEG.
V5V
Analog +5V supply for the signal processing section. This pin is referenced to VGND. For voltages less than 4V,
the under voltage lockout circuit will keep the part in sleep mode. De-coupling capacitance should be placed
between this pin and VGND.
PP
AA
CC
KK
AA
GG
EE
DD
AA
TT
AA
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