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參數(shù)資料
| 型號(hào)： | LX1801CLQ-TR |
| 廠商： | MICROSEMI CORP |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC16 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MLPQ-16 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 255K |
| 代理商： | LX1801CLQ-TR |
LX1801
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
Copyright
2005
Rev. 1.0, 5/4/2006
WWW
.Microse
m
i
.CO
M
SMBus to Analog & Digital System Interface
TM
TH EORY OF O PERAT ION
BASIC FUNCTIONALITY
The LX1801 contains three 8 bit DAC’s, an 8 bit ADC and a
SMBus interface with 7 addressable registers to control 5 dimming
modes for a notebook backlight inverter. The ADC contains a track
and hold input that stores the analog voltage level while the
conversion is being processed.
Several special circuits are also
present in the LX1801. Analog comparators and a 2 bit R/S register
detect and latch inverter fault conditions. Another analog comparator
monitors real time on / off status of the CCFL lamp and writes it,
along with inverter fault status to a host readable register.
An analog multiplier provides the ability for implementing Intel
TM
DPST (Display Power Savings Technology), and voltage limiting
clamps on the ALS input provide SMBus programmable range
limiting of the ambient light sensor output signal.
SMBUS INTERFACE
The LX1801 communicates over the SMBus in the slow speed
Low Power Level and operates in a “slave” mode receiving
commands and sending and receiving data from the host or bus
“master”. The LX1801 can be configured for one of two addresses
by connecting the ADR0 input to 5V or ground. Addresses 0x58
and 0x5A can be selected with the strapping code below:
Table 1. Address strapping codes
Option #
ADR 0
Hex Address
1
0V
:058
2
5V
:05A
APPLICATION NOTE
LAYOUT GUIDELINES
The LX1801 is sensitive to noise at the analog input pins so these
nodes should be a low impedance path to ground for high frequency
noise. As a precaution, the BRITE_OUT and ALS _IN pins should
be routed away from digital switching traces and have ceramic
capacitors located close to the package pins. The VDD Pin should be
decoupled to ground with a 0.1uF ceramic capacitor located as close
as possible to the IC.
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