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LX1801
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
Copyright
2005
Rev. 1.0, 5/4/2006
WWW
.Microse
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i
.CO
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SMBus to Analog & Digital System Interface
TM
APPLICATION NOTE
SMBus De-featuring
Packet Error Correction (PEC) and the Alarm function are not supported.
DEVICE ADDRESS:
In this document the device address is always expressed as a full 8 bit address. The high nibble of the address is always 5H. In the low nibble
bit 0 is always the R/W bit, and bits 3-1 are A2, A1, and A0. This device implements one address strap at A0. When this strap is grounded
the resulting device address is 58(H); when pulled to 5V, the resulting device address is 5A(H). The state of the A0 strap is sensed at Power
on reset. The pin will not change state when the system is in operation.
REGISTER DEFINITIONS:
BIT DEFINITIONS
DESCRIPTION
ADDR TYPE
7
6
5
4
3
2
1
0
BRIGHTNESS
CONTROL
0x00
R/W
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
DEVICE
CONTROL
0x01
R/W
RESRV
D
RESRVD
ALS DLY1
(OPTION)
ALS DLY0
(OPTION)
ALS_CTL
PWM_MD PWM_SEL
LMP_CTL
FAULT / STATUS
0x02
R/O
RESRVD
LMP_ST
1= LAMP
IS ON
OV_CUR
1= OVER
CURENT
THR_SD
1= OVER
TEMP
FAULT
1= ANY
FAULT
IDENTIFICATION
0x03
R/O
MFG4
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
ALS STATUS
0x04
R/O
ALS7
ALS6
ALS5
ALS4
ALS3
ALS2
ALS1
ALS0
ALS LOW LIMIT
0x05
R/W
ALSLL7
ALSLL6
ALSLL5
ALSLL4
ALSLL3
ALSLL2
ALSLL1
ALSLL0
ALS HIGH LIMIT
0x06
R/W
ALSHL7
ALSHL6
ALSHL5
ALSHL4
ALSHL3
ALSHL2
ALSHL1
ALSHL0
Specific requirements for Register 0:
1.
A Write Byte cycle shall set the brightness level if the IC is in SMBus mode as selected by bits 3-1 of the Device control register.
2.
A Write Byte cycle shall have no effect on the BRITE_OUT pin when the IC is not in the SMBus mode.
3.
A Read Byte cycle shall return the current brightness level regardless of the value of PWM_SEL.
4.
When in SMBus or SMBus + DPST mode, register 0x00 must reflect exactly the last value written to it via the SMBus, not a
digitized version of the analog brightness control output voltage. If DPST is active a read to register 0x00 shall not include its
affect.
5.
When the PWM or ALS or ALS+DPST mode is set, register 0x00 reads will return the digitized DC brightness control voltage
exclusive of any offset produced from the V_BOT input. Range of the read voltage is from zero to VREF_IN.
6.
A value of 0xFF shall set the BRITE_OUT level to maximum brightness.
7.
A value of 0x00 shall set the BRITE_OUT level to minimum brightness.
8.
The default value shall be 0xFF.
Specific requirements for Register 4:
1.
Register 0x04 reads always produce the digitized raw ALS_IN voltage, independent of what mode has been set. This data will not
include the effect of DPST if DPST is active, or the effect of the high and low limit registers.
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