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參數(shù)資料
| 型號(hào)： | LXT300Z |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | ADVANCED T1/E1 SHORT-HAUL TRANSCEIVERS |
| 中文描述： | 先進(jìn)的T1/E1短途收發(fā)器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 508K |
| 代理商： | LXT300Z |
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The LXT300Z and LXT301Z are fully integrated PCM
transceivers for both 1.544 Mbps (DSX-1) and 2.048
Mbps (E1) applications. Both transceivers allow full-
duplex transmission of digital data over existing twisted-
pair installations. The first page of this data sheet shows a
simplified block diagram of the LXT300Z; Figure 2
shows the LXT301Z. The LXT301Z is similar to the
LXT300Z, but does not incorporate the Jitter Attenuator
and associated Elastic Store, or the serial interface port.
The LXT300Z and LXT301Z transceivers each interface
with two twisted-pair lines (one twisted-pair for transmit,
one twisted-pair for receive) through standard pulse trans-
formers and appropriate resistors.
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The LXT300Z and LXT301Z are low-power CMOS
devices. Each operates from a single +5 V power supply
which can be connected externally to both the transmitter
and receiver. However, the two inputs must be within ± .3V
of each other, and decoupled to their respective grounds
separately. Refer to Application Information for typical
decoupling circuitry. Isolation between the transmit and
receive circuits is provided internally.
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Upon power up, the transceiver is held static until the
power supply reaches approximately 3 V. Upon crossing
this threshold, the device begins a 32 ms reset cycle to cal-
ibrate the transmit and receive delay lines and lock the
Phase Lock Loop to the receive line. A reference clock is
required to calibrate the delay lines. The transmitter refer-
ence is provided by TCLK. MCLK provides the receiver
reference for the LXT301Z. The crystal oscillator pro-
vides the receiver reference in the LXT300Z. If the
LXT300Z crystal oscillator is grounded, MCLK is used as
the receiver reference clock.
The transceiver can also be reset from the Host or Hard-
ware Mode. In Host Mode, reset is commanded by simul-
taneously writing RLOOP and LLOOP to the register. In
Hardware Mode, reset is commanded by holding RLOOP
and LLOOP High simultaneously for 200 ns. Reset is ini-
tiated on the falling edge of the reset request. In either
mode, reset clears and sets all registers to 0 and then begins
calibration.
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相關(guān)PDF資料 |
PDF描述 |
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| LXT301Z | ADVANCED T1/E1 SHORT-HAUL TRANSCEIVERS |
| LXT304A | Low-Power T1/E1 Short-Haul Transceiver with Receive JA |
| LXT305A | Integrated T1/E1 Short-Haul Transceiver wtih Transmit JA |
| LXC6176 | 39513254 |
| LXC8192 | Integrated T1/E1 Short-Haul Transceiver wtih Transmit JA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LXT300ZNE | 制造商:Intel 功能描述:ELECTRONIC COMPONENT |
| LXT300ZPE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
| LXT301JE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| LXT301NE | 制造商:Level One 功能描述:DATACOM, PCM TRANSCEIVER, PDIP28 |
| LXT301Z | 制造商:LVL1 制造商全稱:LVL1 功能描述:ADVANCED T1/E1 SHORT-HAUL TRANSCEIVERS |
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