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參數(shù)資料
| 型號： | LXT304A |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | Low-Power T1/E1 Short-Haul Transceiver with Receive JA |
| 中文描述： | 低功耗的T1/E1短途收發(fā)器接收JA |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 347K |
| 代理商： | LXT304A |
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The Host Mode provides a latched Interrupt output (INT)
which is triggered by a change in the Loss of Signal (LOS)
and/or Driver Performance Monitor (DPM) bits. The Inter-
rupt is cleared when the interrupt condition no longer
exists, and the host processor enables the respective bit in
the serial input data byte. Host Mode also allows control of
the serial data and receive data output timing. The Clock
Edge (CLKE) signal determines when these outputs are
valid, relative to the Serial Clock (SCLK) or RCLK as
listed in Table 3.
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