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參數(shù)資料
| 型號(hào)： | LXT381LE |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Octal E1 Line Interface Unit |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封裝： | LQFP-144 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LXT381LE |
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LXT381
—
Octal E1 Line Interface
18
Datasheet
3.0
JTAG Boundary Scan
3.1
Overview
The LXT381 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy
access to the interface pins for board testing purposes.
In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT381 also
includes analog test port capabilities. This feature provides access to the TIP and RING signals in
each channel (transmit and receive.) This way, the signal path integrity across the primary winding
of each coupling transformer can be tested.
3.2
Architecture
Figure 6
represents the LXT381 basic JTAG architecture.
The LXT381 JTAG architecture includes a TAP Test Access Port Controller, data registers and an
instruction register. The following paragraphs describe these blocks in detail.
Figure 6. LXT381 JTAG Architecture
MUX
TDO
TAP
Controller
TCK
TMS
TRST
TDI
Boundry Scan Data Register
BSR
Analog Port Scan Register
ASR
Device Identification Register
IDR
Bypass Register
BYR
Instruction Register
IR
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