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參數(shù)資料
| 型號(hào)： | M1021-13I173.3708 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 440K |
| 代理商： | M1021-13I173.3708 |
M1020/21 Datasheet Rev 1.0
7
of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
M1020/21
VCSO B
ASED
C
LOCK
PLL
P r o d u c t D a t a S h e e t
Circuit See Table 6, Example External Loop Filter Component Values on pg. 7.
PLL bandwidth is affected by loop filter component
values, the “M” value, and the “PLL Loop Constants”
listed in AC Characteristics on pg. 9.
The
MR_SEL3:0
settings can be used to actively change
PLL loop bandwidth in a given application. See “M and
R Divider Look-Up Tables (LUT)” on pg. 3.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
Example External Loop Filter Component Values
1
for M1020-yz-155.5200 and
M1021-yz-155.5200
VCSO Parameters: K
VCO
= 200kHz/V, R
IN
= 100k
(pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
F
REF
(MHz)
(MHz)
19.44
2
155.52
0 0 0 0
8
38.88
3
155.52
0 0 0 1
16
77.76
4
155.52
0 1 0 1
8
77.76
5
155.52
0 1 1 0
32
155.52
4
155.52
1 0 1 0
16
155.52
5
155.52
1 0 1 1
64
Example External Loop Filter Comp. Values
R
LOOP
C
LOOP
Nominal Performance Using These Values
PLL Loop
Bandwidth
Factor
315
Hz
270
Hz
315
Hz
250
Hz
270
Hz
266
Hz
Table 6: Example External Loop Filter Component Values
F
VCSO
MR_SEL3:0 MDiv NBW
R
POST
C
POST
Damping
Passband
Peaking
(dB)
0.07
0.05
0.07
0.05
0.05
0.05
0
0
0
0
0
0
6.8
k
12
k
6.8
k
22
k
12
k
47
k
10
μ
F
10
μ
F
10
μ
F
4.7
μ
F
10
μ
F
2.2
μ
F
82
k
82k
82k
82k
82k
82k
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
5.4
6.7
5.4
6.0
6.7
6.2
Note 1: K
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: This row is for the M1020 only.
Note 3: This row is for the M1021 only.
Note 4: Optimal for system clock filtering.
Note 5: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
A
BSOLUTE
M
AXIMUM
R
ATINGS1
Symbol Parameter
V
I
V
O
V
CC
T
S
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
R
ECOMMENDED
C
ONDITIONS
OF
O
PERATION
Rating
-
0.5
to V
CC
+
0.5
-
0.5
to V
CC
+
0.5
Unit
Inputs
V
Outputs
V
Power Supply Voltage
4.6
V
Storage Temperature
-
45
to +
100
o
C
Table 7: Absolute Maximum Ratings
Symbol Parameter
V
CC
Positive Supply Voltage
T
A
Ambient Operating Temperature
Min
3.135
Typ
3.3
Max
3.465
Unit
V
Commercial
Industrial
0
+
70
+
85
o
C
o
C
-40
Table 8: Recommended Conditions of Operation
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